Renesas R5S72641 User Manual

 
Section 26   USB 2.0 Host/Function Module 

Page 1360 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

4 

UACT 

0 

R/W 

USB Bus Enable 

Enables operation of the USB bus (controls the SOF 
or 

SOF packet transmission to the USB bus) when 

the host controller function is selected.  

0:  Downstream port is disabled (SOF/

SOF 

transmission is disabled). 

1:  Downstream port is enabled (SOF/

SOF 

transmission is enabled). 

With this bit set to 1, this module puts the USB port 
to the USB-bus enabled state and performs SOF 
output and data transmission and reception. 

This module starts outputting SOF/

SOF within 1 () 

frame after 1 has been written to UACT.  

With this bit set to 0, this module enters the idle state 
after outputting SOF/

SOF.  

This module sets this bit to 0 on any of the following 
conditions. 

  A DTCH interrupt is detected during 

communication (while UACT = 1). 

  An EOFERR interrupt is detected during 

communication (while UACT = 1). 

Writing 1 to this bit should be done at the end of the 
USB bus reset process (writing 0 to USBRST) or at 
the end of the resume process from the suspended 
state (writing 0 to RESUME). 

This bit should be set to 0 if the function controller 
function is selected. 

3 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0.