Renesas R5S72641 User Manual

 
Section 26   USB 2.0 Host/Function Module 

Page 1422 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

8 SQCLR  0 R/W*

1

 

Toggle Bit Clear 

Specifies DATA0 as the expected value of the 
sequence toggle bit for the next transaction during 
the DCP transfer. 

0: Invalid 

1: Specifies DATA0. 

This bit always indicates 0. 

Do not set the SQCLR and SQSET bits to 1 
simultaneously. 

Set this bit to 1 while CSCTS is 0 and PID is NAK.  

Before setting this bit to 1 after modifying the PID 
bits for the DCP from BUF to NAK, check that 
CSSTS and PBUSY are 0. 

However, if the PID bits have been modified to NAK 
by this module, checking PBUSY is not necessary. 

7 SQSET  0 R/W*

1

 

Toggle Bit Set 

Specifies DATA1 as the expected value of the 
sequence toggle bit for the next transaction during 
the DCP transfer. 

0: Invalid 

1: Specifies DATA1. 

Do not set the SQCLR and SQSET bits to 1 
simultaneously. 

Set this bit to 1 while CSSTS is 0 and PID is NAK. 

Before setting this bit to 1 after modifying the PID 
bits for the DCP from BUF to NAK, check that 
CSSTS and PBUSY are 0. 

However, if the PID bits have been modified to NAK 
by this module, checking PBUSY is not necessary.