Renesas R5S72641 User Manual
R01UH0134EJ0400 Rev. 4.00
Page xv of xl
Sep 24, 2014
Section 8 Cache ................................................................................................. 209
8.1
Features ............................................................................................................................. 209
8.1.1
Cache Structure ................................................................................................. 209
8.2
Register Descriptions ........................................................................................................ 212
8.2.1
Cache Control Register 1 (CCR1) .................................................................... 212
8.2.2
Cache Control Register 2 (CCR2) .................................................................... 214
8.3
Operation .......................................................................................................................... 218
8.3.1
Searching Cache ............................................................................................... 218
8.3.2
Read Access ...................................................................................................... 220
8.3.3
Prefetch Operation (Only for Operand Cache) ................................................. 220
8.3.4
Write Operation (Only for Operand Cache) ...................................................... 221
8.3.5
Write-Back Buffer (Only for Operand Cache) .................................................. 221
8.3.6
Coherency of Cache and External Memory or
Large-Capacity
On-Chip RAM ......................................................................... 223
8.4
Memory-Mapped Cache ................................................................................................... 224
8.4.1
Address Array ................................................................................................... 224
8.4.2
Data Array ........................................................................................................ 225
8.4.3
Usage Examples ................................................................................................ 227
8.4.4
Usage Notes ...................................................................................................... 228
Section 9 Bus State Controller ........................................................................... 229
9.1
Features ............................................................................................................................. 229
9.2
Input/Output Pins .............................................................................................................. 232
9.3
Area Overview .................................................................................................................. 234
9.3.1
Address Map ..................................................................................................... 234
9.3.2
Data Bus Width and Endian Specification of Each Area and
Related Pin Settings Depending on Boot Mode ................................................ 235
9.4
Register Descriptions ........................................................................................................ 237
9.4.1
Common Control Register (CMNCR) .............................................................. 239
9.4.2
CSn Space Bus Control Register (CSnBCR) (n = 0 to 6) ................................. 242
9.4.3
CSn Space Wait Control Register (CSnWCR) (n = 0 to 6) .............................. 247
9.4.4
SDRAM Control Register (SDCR) ................................................................... 280
9.4.5
Refresh Timer Control/Status Register (RTCSR) ............................................. 284
9.4.6
Refresh Timer Counter (RTCNT) ..................................................................... 286
9.4.7
Refresh Time Constant Register (RTCOR) ...................................................... 287
9.4.8
AC Characteristics Switching Register (ACSWR) ........................................... 288
9.4.9
AC Characteristics Switching Key Register (ACKEYR) ................................. 289
9.4.10
Sequence to Write to ACSWR .......................................................................... 290
9.5
Operation .......................................................................................................................... 291