Renesas R5S72641 User Manual
Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00
Page 141 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Note in Manual Reset
When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the
bus is released or during burst transfer by the direct memory access controller, manual reset
exception handling will be deferred until the CPU acquires the bus. The CPU and the BN bit in
IBNR of the interrupt controller are initialized by a manual reset. The FPU and other modules are
not initialized.
bus is released or during burst transfer by the direct memory access controller, manual reset
exception handling will be deferred until the CPU acquires the bus. The CPU and the BN bit in
IBNR of the interrupt controller are initialized by a manual reset. The FPU and other modules are
not initialized.