Renesas R5S72641 User Manual
Section 33 Power-Down Modes
Page 1814 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Canceling by a source other than a reset
When the falling or rising edge of the NMI pin (selected by a corresponding bit in DSESR) or
falling or rising edge of the pins for canceling (selected by a corresponding bit in DSESR) is
detected or the realtime clock alarm interrupt (see section 14.4.4, Alarm Function) is
generated, clock oscillation is started after the wait time for the oscillation settling time. After
the oscillation settling time has elapsed, deep standby mode is cancelled and the power-on
reset exception handling is executed.
falling or rising edge of the pins for canceling (selected by a corresponding bit in DSESR) is
detected or the realtime clock alarm interrupt (see section 14.4.4, Alarm Function) is
generated, clock oscillation is started after the wait time for the oscillation settling time. After
the oscillation settling time has elapsed, deep standby mode is cancelled and the power-on
reset exception handling is executed.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the
falling edge of the NMI pin, the NMI pin should be high when deep standby mode is entered
(when the clock pulse stops) and should be low when deep standby mode is canceled (when
the clock is initiated after the oscillation settling). When deep standby mode is canceled by the
rising edge of the NMI pin, the NMI pin should be low when deep standby mode is entered
(when the clock pulse stops) and should be high when deep standby mode is canceled (when
the clock is initiated after the oscillation settling). (This is the same with the pins for
canceling.)
interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the
falling edge of the NMI pin, the NMI pin should be high when deep standby mode is entered
(when the clock pulse stops) and should be low when deep standby mode is canceled (when
the clock is initiated after the oscillation settling). When deep standby mode is canceled by the
rising edge of the NMI pin, the NMI pin should be low when deep standby mode is entered
(when the clock pulse stops) and should be high when deep standby mode is canceled (when
the clock is initiated after the oscillation settling). (This is the same with the pins for
canceling.)
Also, the NMI and all the pins which are selected by DSSSR to cancel deep standby mode
should be the following pin levels when the CPU enters deep standby, regardless whether they
will really cancel deep standby mode or not.
should be the following pin levels when the CPU enters deep standby, regardless whether they
will really cancel deep standby mode or not.
The pins that are set as rising edge should be low when the CPU enters deep standby mode.
The pins that are set as falling edge should be high when the CPU enters deep standby
mode.
mode.
Canceling with a reset
Driving the
RES pin low cancels deep standby mode and causes a transition to the power-on
reset state. After this, driving the
RES pin high initiates power-on reset exception handling.
Output of the internal clock from the CKIO pin also starts by driving the
RES pin low.
Keep the
RES pin low until the clock oscillation has settled.