Renesas R5S72641 User Manual
Section 8 Cache
R01UH0134EJ0400 Rev. 4.00
Page 215 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 17
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
16 LE
0 R/W
Lock
Enable
Controls the cache locking function.
0: Not cache locking mode
1: Cache locking mode
15 to 10
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
9
8
W3LOAD*
W3LOCK
0
0
R/W
R/W
Way 3 Load
Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
7 to 2
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
1
0
W2LOAD*
W2LOCK
0
0
R/W
R/W
Way 2 Load
Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK =1 in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
while W2LOAD = 1 and W2LOCK =1 in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.