Renesas R5S72641 User Manual

 

Section 11   Multi-Function Timer Pulse Unit 2 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 489 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

3 TOCL  0  R/(W)*

3

TOC Register Write Protection*

1

 

This bit selects the enable/disable of write access to the 
TOCS, OLSN, and OLSP bits in TOCR1. 

0: Write access to the TOCS, OLSN, and OLSP bits is 

enabled 

1: Write access to the TOCS, OLSN, and OLSP bits is 

disabled 

2 TOCS  0  R/W 

TOC 

Select 

This bit selects either the TOCR1 or TOCR2 setting to 
be used for the output level in complementary PWM 
mode and reset-synchronized PWM mode. 

0: TOCR1 setting is selected 

1: TOCR2 setting is selected 

1 

OLSN 

0 

R/W 

Output Level Select N*

2

*

4

 

This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode. 
See table 11.28. 

0 

OLSP 

0 

R/W 

Output Level Select P*

2

 

This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode. 
See table 11.29. 

Notes:  1.  Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of 

control. 

 

2.  Clearing the TOCS0 bit to 0 makes this bit setting valid. 

 

3.  After power-on reset, 1 can be written only once. After 1 has been written, 0 cannot be 

written. 

 

4.  If there is no dead time, the reverse phase output is the inversion of the forward phase. 

Set OLSP and OLSN to the same value.