Renesas R5S72641 User Manual

Page of 2152
 
 
Section 16   Renesas Serial Peripheral Interface 
 
 
Page 800 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
16.3.13
  Command Register (SPCMD) 
Each channel has four command registers (SPCMD0 to SPCMD3). SPCMD0 to SPCMD3 are 
used to set a transfer format for master mode operation. Some of the bits in SPCMD0 are used to 
set a transfer mode for slave mode operation. In master mode, this module sequentially references 
SPCMD0 to SPCMD3 according to the settings in bits SPSLN1 and SPSLN0 in the sequence 
control register (SPSCR), and executes the serial transfer that is set in the referenced SPCMD. 
While bit TEND in the status register (SPSR) indicates that transmission is not completed, correct 
operation of this module cannot be guaranteed if SPCMD is changed that is referred by this 
module. SPCMD referenced by this module in master mode can be checked by means of bits 
SPCP1 and SPCP0 in the sequence status register (SPSSR). When the function of this module in 
master mode is enabled, operation cannot be guaranteed if the value set in SPCMD0 is changed. 
15
14
13
12
11
10
9
8
Bit:
Initial value:
R/W:
0
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCK 
DEN
SLN 
DEN
SPN 
DEN
LSBF
SPB3
SPB2
SPB1
SPB0
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
1
1
0
1
R/W
R
R
R
R/W
R/W
R/W
R/W
SSLKP
BRDV1 BRDV0 CPOL
CPHA
 
 
Bit Bit 
Name 
Initial 
Value R/W Description 
15 SCKDEN 
0  R/W 
RSPCK Delay Setting Enable 
Sets the period from the point this module in master 
mode activates the SSL signal until the RSPCK 
starts oscillation (RSPCK delay). If the SCKDEN bit 
is 0, this module sets the RSPCK delay to 1 RSPCK. 
If the SCKDEN bit is 1, this module starts the 
oscillation of RSPCK at an RSPCK delay in 
compliance with the clock delay register (SPCKD) 
settings.  
To use this module in slave mode, the SCKDEN bit 
should be set to 0. 
0: An RSPCK delay of 1 RSPCK 
1: An RSPCK delay equal to SPCKD settings.