Intel 2 Quad Q8400S AT80580PJ0674ML User Manual
Product codes
AT80580PJ0674ML
Datasheet
33
Electrical Specifications
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 400 MHz BCLK[1:0].
frequencies based on a 400 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -100 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +100 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
specification as governed by the period stability specification (T2). Min period specification
is based on -100 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +100 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
4.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Measurement taken from differential waveform.
6.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
7.
Duty Cycle (High time/Period) must be between 40 and 60%
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
frequencies based on a 333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Measurement taken from differential waveform.
5.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6.
Duty Cycle (High time/Period) must be between 40% and 60%.
Table 2-17. FSB Differential Clock Specifications (1600 MHz FSB)
T# Parameter
Min
Nom
Max
Unit
Figure Notes
1
BCLK[1:0] Frequency
397.962
-
400.037
MHz
-
T1: BCLK[1:0] Period
2.499766
-
2.512800
ns
2
T2: BCLK[1:0] Period Stability
-
-
150
ps
3, 4, 7
T5: BCLK[1:0] Rise and Fall Slew
Rate
Rate
2.5
-
8
V/ns
5
Slew Rate Matching
N/A
N/A
20
%
-
6
Table 2-18. FSB Differential Clock Specifications (1333 MHz FSB)
T# Parameter
Min
Nom
Max
Unit
Figure Notes
1
BCLK[1:0] Frequency
331.633
—
333.367
MHz
-
6
T1: BCLK[1:0] Period
2.99970
—
3.01538
ns
2
T2: BCLK[1:0] Period Stability
—
—
150
ps
3
T5: BCLK[1:0] Rise and Fall Slew Rate
2.5
—
8
V/ns
4
Slew Rate Matching
N/A
N/A
20
%
-
5