Intel 2 Quad Q8400S AT80580PJ0674ML User Manual
Product codes
AT80580PJ0674ML
Land Listing and Signal Descriptions
64
Datasheet
4.2
Alphabetical Signals Reference
Table 4-3.
Signal Description (Sheet 1 of 10)
Name
Type
Description
A[35:3]#
Input/
Output
A[35:3]# (Address) define a 2
36
-byte physical memory address
space. In sub-phase 1 of the address phase, these signals
transmit the address of a transaction. In sub-phase 2, these
signals transmit transaction type information. These signals must
connect the appropriate pins/lands of all agents on the processor
FSB. A[35:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See
transmit the address of a transaction. In sub-phase 2, these
signals transmit transaction type information. These signals must
connect the appropriate pins/lands of all agents on the processor
FSB. A[35:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See
for more details.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must
be valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must
be valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All
bus agents observe the ADS# activation to begin protocol
checking, address decode, internal snoop, or deferred reply ID
match operations associated with the new transaction.
transaction address on the A[35:3]# and REQ[4:0]# signals. All
bus agents observe the ADS# activation to begin protocol
checking, address decode, internal snoop, or deferred reply ID
match operations associated with the new transaction.
ADSTB[1:0]#
Input/
Output
Address strobes are used to latch A[35:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals
as shown below.
their rising and falling edges. Strobes are associated with signals
as shown below.
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing V
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing V
CROSS
.
BNR#
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any
bus agent unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
bus agent unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#