Intel 2 Duo T9900 AW80576GH0836MG User Manual

Datasheet

3

Introduction ..............................................................................................................7
1.1

Terminology .......................................................................................................8

Low Power Features ................................................................................................ 11
2.1

Clock Control and Low-Power States .................................................................... 11
2.1.1

Core Low-Power State Descriptions........................................................... 13
2.1.1.1

Core C0 State........................................................................... 13

Core C1/AutoHALT Powerdown State ........................................... 13

Normal State............................................................................ 15

Stop-Grant State ...................................................................... 15

Stop-Grant Snoop State............................................................. 16

Sleep State .............................................................................. 16

Deep Sleep State ...................................................................... 16

Enhanced Intel SpeedStep® Technology .............................................................. 19

Electrical Specifications ........................................................................................... 25
3.1

Power and Ground Pins ...................................................................................... 25

Decoupling Guidelines........................................................................................ 25
3.2.1

 

Decoupling...................................................................................... 25

FSB AGTL+ Decoupling ........................................................................... 25

FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 25

Voltage Identification and Power Sequencing ........................................................ 26

Reserved and Unused Pins.................................................................................. 29

FSB Signal Groups............................................................................................. 30

CMOS Signals ................................................................................................... 31

Maximum Ratings.............................................................................................. 31

3.10 Processor DC Specifications ................................................................................ 32

Package Mechanical Specifications and Pin Information .......................................... 51
4.1

Alphabetical Signals Reference ............................................................................ 93

Thermal Specifications and Design Considerations ................................................ 101
5.1

Monitoring Die Temperature ............................................................................. 108
5.1.1

Thermal Diode ..................................................................................... 108