Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Register Description
114
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
Channel Rank Limit Range Registers.
2.17.2
MC_RIR_WAY_CH0_0
MC_RIR_WAY_CH0_1
MC_RIR_WAY_CH0_2
MC_RIR_WAY_CH0_3
MC_RIR_WAY_CH0_4
MC_RIR_WAY_CH0_5
MC_RIR_WAY_CH0_6
MC_RIR_WAY_CH0_7
MC_RIR_WAY_CH0_8
MC_RIR_WAY_CH0_9
MC_RIR_WAY_CH0_10
MC_RIR_WAY_CH0_11
MC_RIR_WAY_CH0_12
MC_RIR_WAY_CH0_13
MC_RIR_WAY_CH0_14
MC_RIR_WAY_CH0_15
MC_RIR_WAY_CH0_16
MC_RIR_WAY_CH0_17
MC_RIR_WAY_CH0_18
MC_RIR_WAY_CH0_19
MC_RIR_WAY_CH0_20
MC_RIR_WAY_CH0_21
MC_RIR_WAY_CH0_22
MC_RIR_WAY_CH0_23
MC_RIR_WAY_CH0_24
MC_RIR_WAY_CH0_25
MC_RIR_WAY_CH0_26
MC_RIR_WAY_CH0_27
MC_RIR_WAY_CH0_28
MC_RIR_WAY_CH0_29
MC_RIR_WAY_CH0_30
MC_RIR_WAY_CH0_31
Channel Rank Interleave Way Range Registers. These registers allow the user to define 
the ranks and offsets that apply to the ranges defined by the LIMIT in the 
MC_RIR_LIMIT_CH registers. The mappings are as follows:
RIR_LIMIT_CH{chan}[0] -> RIR_WAY_CH{chan}[3:0] 
Device:
4
Function: 2
Offset:
40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch
Access as a Dword
Bit
Type
Reset
Value
Description
9:0
RW
0
LIMIT. This specifies the top of the range being mapped to the ranks specified 
in the MC_RIR_WAY_CH registers. The most significant bits of the lowest 
address in this range is one greater than the limit field in the RIR register with 
the next lower index. This field is compared against MA[37:28].