Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
15
Introduction
1
Introduction
The Intel® Xeon® Processor 5500 Series is the first generation DP server/workstation 
processor to implement key new technologies:
• Integrated Memory Controller
• Point-to-point link interface based on Intel® QuickPath Interconnect (Intel® QPI). 
Reference to this interface may sometimes be abbreviated with Intel QPI 
throughout this document.
The processor is optimized for performance with the power efficiencies of a low-power 
microarchitecture to enable smaller, quieter systems.
This document provides register documentation and functional description of major 
functional areas of the processor non-core design such as the memory controller and 
Intel QPI logic, and additional features pertinent to implementation and operation of 
the processor.
The Intel Xeon Processor 5500 Series are multi-core processors, based on 45 nm 
process technology. Processor features vary by SKU and include up to two Intel 
QuickPath Interconnect point to point links capable of up to 6.4 GT/s, up to 8 MB of 
shared cache, and an integrated memory controller. The processors support all the 
existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) 
and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced 
Technologies: Execute Disable Bit, Intel
®
 64 Technology, Enhanced Intel
®
 SpeedStep 
Technology, Intel
®
 Virtualization Technology (Intel
®
 VT), and Intel
®
 Hyper-Threading 
Technology.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in 
the active state when driven to a low level. For example, when RESET# is low, a reset 
has been requested.
1.1.1
Processor Terminology
Commonly used terms are explained here for clarification:
• DDR3 — Double Data Rate 3 synchronous dynamic random access memory 
(SDRAM) is the name of the new DDR memory standard that is being developed as 
the successor to DDR2 SDRAM.
• Enhanced Intel SpeedStep
®
 Technology — Enhanced Intel SpeedStep 
Technology allows trade-offs to be made between performance and power 
consumption.
• Execute Disable Bit — Execute Disable allows memory to be marked as 
executable or non-executable, when combined with a supporting operating system. 
If code attempts to run in non-executable memory the processor raises an error to 
the operating system. This feature can prevent some classes of viruses or worms 
that exploit buffer over run vulnerabilities and can thus help improve the overall 
security of the system. See the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual 
 for more detailed information. Refer to 
http://developer.intel.com/
 for future reference on up to date nomenclatures.