Intel Xeon E5502 80602E5502 User Manual

Product codes
80602E5502
Page of 130
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
53
Register Description
2.6.7
MC_CFG_CONTROL
This register locks and unlocks write access to the Uncore configuration. BIOS must 
write a “1” to the MC_CFG_LOCK bit after reset to allow the Integrated Memory 
Controller to start accepting requests. It may subsequently be unlocked by writing a 
“1” to the MC_CFG_UNLOCK bit and a “0” to the MC_CFG_LOCK bit without affecting 
memory traffic.
2.6.8
POWER_CNTRL_ERR_STATUS
Power management Error Status register. 
Device:
0
Function: 0
Offset:
90h
Access as a Dword
Bit
Type
Reset
Value
Description
1
WO
0
MC_CFG_UNLOCK. Unlocks Integrated Memory Controller configuration 
registers without CPU reset. This bit does NOT unlock any other lock type 
without a CPU reset. 
0
WO
0
MC_CFG_LOCK. Locks Integrated Memory Controller configuration registers. 
Writes are no longer allowed to the configuration registers.
Device:
0
Function: 0
Offset:
B0h
Access as a Qword
Bit
Type
Reset
Value
Description
63
RO
-
VAL. MC7_STATUS Register Valid. Indicates if the register is valid.
0: Not Valid
1: Valid
62
RO
-
OVER. Machine Check Overflow Flag. Indicates (when set) that a 
machine-check error occurred while the results of a previous error were still 
in the error-reporting register bank (that is, the VAL bit was already set in 
the IA32_MC7_STATUS register). The processor sets the OVER flag and 
software is responsible for clearing it. In general, enabled errors are written 
over disabled errors, and uncorrected errors are written over corrected 
errors. Uncorrected errors are not written over previous valid uncorrected 
errors.
0: No Overflow
1: Overflow
61
RO
-
UC. Error Uncorrected Flag. Indicates (when set) that the processor did not 
or was not able to correct the error condition. When cleared, this flag 
indicates that the processor was able to correct the error condition.
0: Corrected
1: Uncorrected
60
RO
-
EN. Error Enabled Flag. Indicates (when set) that the error was enabled by 
the associated EEj bit of the IA32_MC7_CTL register.
0: Not Enabled
1: Enabled