Intel IXF1104 User Manual
Intel
®
IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
The Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as
the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC
supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or
ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or
ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
The copper PHY interface supports the standard and reduced pin-count Gigabit Media
Independent Interface (GMII and RGMII) for high-port-count applications. For fiber
applications the integrated Serializer/Deserializer (SerDes) on each port supports direct
connection to optical modules to reduce PCB area requirements and system cost.
Independent Interface (GMII and RGMII) for high-port-count applications. For fiber
applications the integrated Serializer/Deserializer (SerDes) on each port supports direct
connection to optical modules to reduce PCB area requirements and system cost.
Product Features
Applications
Four Independent Ethernet MAC Ports for
Copper or Fiber Physical layer connectivity.
Copper or Fiber Physical layer connectivity.
— IEEE 802.3 compliant
— Independent Enable/Disable of any port
— Independent Enable/Disable of any port
Copper Mode:
— RGMII for 10/100/1000 Mbps links
— GMII for 1000 Mbps full-duplex links
— IEEE 802.3 MDIO interface
— GMII for 1000 Mbps full-duplex links
— IEEE 802.3 MDIO interface
Fiber Mode:
— Integrated SerDes interface for direct
connection to 1000BASE-X optical modules
— IEEE 802.3 auto-negotiation or forced mode
— Supports SFP MSA-compatible transceivers
— Supports SFP MSA-compatible transceivers
SPI3 interface supports data transfers up to
4 Gbps in both modes:
4 Gbps in both modes:
— 32-bit Multi-PHY mode (133 MHz)
— 4 x 8-bit Single-PHY mode (125 MHz)
— 4 x 8-bit Single-PHY mode (125 MHz)
IEEE 802.3-compliant Flow Control
— Loss-less up to 9.6 KB packets and 5 km links
— Jumbo frame support for 9.6 KB packets
— Jumbo frame support for 9.6 KB packets
Internal per-channel FIFOs: 32 KB Rx, 10 KB Tx
Flexible 32/16/8-bit CPU interface
Flexible 32/16/8-bit CPU interface
Programmable Packet handling
— Filter broadcast, multicast, unicast, VLAN
and errored packets
— Automatically pad undersized Tx packets
— Remove CRC from Rx packets
— Remove CRC from Rx packets
Performance Monitoring and Diagnostics
— RMON Statistics
— CRC calculation and error detection
— Detection of length error, runt, or overly
— CRC calculation and error detection
— Detection of length error, runt, or overly
large packets
— Counters for dropped and errored packets
— Loopback modes
— JTAG boundary scan
— Loopback modes
— JTAG boundary scan
.18
μ CMOS process technology
— 1.8 V core, 2.5 V RGMII, GMII, OMI, and
3.3 V SPI3 and CPU
Operating Temperature Ranges:
— Copper Mode: -40°C to +85°C
— Fiber Mode:
— Fiber Mode:
0°C to +70°C
Package Options:
— 552-ball Ceramic BGA (standard)
— 552-ball Ceramic BGA (RoHS-compliant)
— 552-ball Plastic FC-BGA (contact your Intel
— 552-ball Ceramic BGA (RoHS-compliant)
— 552-ball Plastic FC-BGA (contact your Intel
Sales Representative)
Load Balancing Systems
MultiService Switches
Web Caching Appliances
Intelligent Backplane Interfaces
Edge Routers
Redundant Line Cards
MultiService Switches
Web Caching Appliances
Intelligent Backplane Interfaces
Edge Routers
Redundant Line Cards
Base Station Controllers and Transceivers
Serving GPRS Support Nodes (SGSN)
Gateway GPRS Support Nodes (GGSN)
Packet Data Serving Nodes (PDSN)
DSL Access Multiplexers (DSLAM)
Cable Modem Termination Systems (CMTS)
Serving GPRS Support Nodes (SGSN)
Gateway GPRS Support Nodes (GGSN)
Packet Data Serving Nodes (PDSN)
DSL Access Multiplexers (DSLAM)
Cable Modem Termination Systems (CMTS)
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005