Nxp Semiconductors ISP1562 User Manual

 

 

AN10050_4 

© NXP B.V.  2007. All rights reserved.

The ISP1562 and the ISP1563 are Hi-Speed Universal Serial Bus (USB) host controllers 
(HCs) that can be directly connected to a standard 32-bit, 33 MHz PCI bus. For the rest 
of this document, they will be known as ‘ISP1562/3’. The ISP1562/3 complies with PCI 
Local Bus Specification Rev. 2.2 and PCI Bus Power Management Interface 
Specification Rev. 1.1. No additional logic is required to implement a complete Hi-Speed 
USB host controller solution on Peripheral Component Interconnect (PCI). 

Adapter cards based on the ISP1562/3 implement three functions: function 0 and 
function 1 for OHCI1 and OHCI2, and function 2 for EHCI. According to PCI Local Bus 
Specification, each physical PCI device may incorporate one to eight separate functions 
(logical devices). Each function contains its own memory-mapped individually 
addressable configuration space of 256 bytes, containing configuration registers. 

The configuration registers of the ISP1562/3 are used by the system’s BIOS and the 
operating system to detect the presence of the respective functions, that is, Vendor ID 
(VID) and Product ID (PID), to determine the necessary resource requirements, that is, 
memory and I/O space, interrupt lines, and so on, and for specific capabilities. 

A set of on-chip ‘operational’ registers is also defined for each of the three host 
controllers implemented in the ISP1562/3. The respective host controller device driver 
interacts with these registers to implement the USB functionality and the legacy support. 
A detailed description of configuration registers and operational registers can be found in 
the ISP1562 and ISP1563 data sheets. 

The ISP1562/3 implements two internal ‘power wells’, V

DD

 and V

DDX

, to benefit from the 

PCI V

AUX

 = 3.3 V dedicated power source, which is present on the PCI connector (pin 

A14) even when PCI V

CC

 = 3.3 V is off. This enables the ISP1562/3 PME# signal to be 

asserted and activates the wake-up logic of the motherboard, even if the rest of the 
system is powered down; for example, in S3

cold

 system standby mode. This is applicable 

mainly to onboard (desktop) or mobile designs, but not applicable to PCI add-on cards 
because the PCI +5 V, used for V

BUS

, is also off during S3

cold

. 

The ISP1562/3 may use PCI V

AUX

 to power its four internal transceivers connected to the 

ISP1562/3 V

DDA_AUX

 (analog), and also the clock circuitry, port router, root hub and Power 

Management Event (PME#) logic connected to the ISP1562/3 

V

CC(I/O)_AUX

 

(digital). 

For details on implementation of the PCB design, see 

Section 4

The power management capabilities enabled by using PCI V

AUX

 allow system designers 

to meet the governmental energy regulations that are becoming increasingly essential 
worldwide: Energy Star/USA: 30 W standby, White Swan/Europe: 5 W standby, Blue 
Angel/Europe: 5 W standby. 

This document provides a description of the application schematics and the PCB design 
recommendations. 

The following sequence is required during the ISP1562/3 initialization, for correct 
functionality: 

1.  Register HcRhDescriptorA = 902h. This means that bit PSM = 1b. 

2.  Register HcControl = 680h. This means that bits HCFS[1:0] = 10b (operational 

mode).