Intel i7-960 AT80601002727AA User Manual
Product codes
AT80601002727AA
Electrical Specifications
14
Datasheet
ensure that the voltage provided to the processor remains within the specifications
listed in
listed in
. Failure to do so can result in timing violations or reduced lifetime of
the processor.
2.3.1
V
CC
, V
TTA
, V
TTD
, V
DDQ
Decoupling
Voltage regulator solutions need to provide bulk capacitance and the baseboard
designer must assure a low interconnect resistance from the regulator to the LGA1366
socket. Bulk decoupling must be provided on the baseboard to handle large current
swings. The power delivery solution must insure the voltage and current specifications
are met (as defined in
designer must assure a low interconnect resistance from the regulator to the LGA1366
socket. Bulk decoupling must be provided on the baseboard to handle large current
swings. The power delivery solution must insure the voltage and current specifications
are met (as defined in
2.4
Processor Clocking (BCLK_DP, BCLK_DN)
The processor core, Intel QPI, and integrated memory controller frequencies are
generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side
bus architecture, there is no direct link between core frequency and Intel QPI link
frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum
core frequency, Intel QPI link frequency and integrated memory controller frequency,
are set during manufacturing. It is possible to override the processor core frequency
setting using software. This permits operation at lower core frequencies than the
factory set maximum core frequency.
generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side
bus architecture, there is no direct link between core frequency and Intel QPI link
frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum
core frequency, Intel QPI link frequency and integrated memory controller frequency,
are set during manufacturing. It is possible to override the processor core frequency
setting using software. This permits operation at lower core frequencies than the
factory set maximum core frequency.
The processor’s maximum non-turbo core frequency is configured during power-on
reset by using values stored internally during manufacturing. The stored value sets the
highest core multiplier at which the particular processor can operate. If lower max non-
turbo speeds are desired, the appropriate ratio can be configured using the
CLOCK_FLEX_MAX MSR.
reset by using values stored internally during manufacturing. The stored value sets the
highest core multiplier at which the particular processor can operate. If lower max non-
turbo speeds are desired, the appropriate ratio can be configured using the
CLOCK_FLEX_MAX MSR.
The processor uses differential clocks (BCLK_DP, BCLK_DN). Clock multiplying within
the processor is provided by the internal phase locked loop (PLL), which requires a
constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum
clocking. The processor core frequency is determined by multiplying the ratio by
133 MHz.
the processor is provided by the internal phase locked loop (PLL), which requires a
constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum
clocking. The processor core frequency is determined by multiplying the ratio by
133 MHz.
2.4.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to
for DC
specifications.
2.5
Voltage Identification (VID)
The voltage set by the VID signals is the reference voltage regulator output voltage to
be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer
to
be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer
to
to temperature and/or current load changes in order to minimize the power of the part.
A voltage range is provided in
A voltage range is provided in
. The specifications have been set such that one
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing such that two devices
at the same core frequency may have different default VID settings. This is reflected by
the VID range values provided in
at the same core frequency may have different default VID settings. This is reflected by
the VID range values provided in
.