Intel i7-960 AT80601002727AA User Manual

Datasheet 

19

1.

Unless otherwise specified, signals have ODT in the package with 50 Ω pulldown to V

SS

.

2.

PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 Ω pullup to V

TT

. 

3.

VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 kΩ to 20 kΩ pulldown 

to V

SS

.

4.

TRST# has ODT in package with a 1 kΩ to 5 kΩ pullup to V

TT

.

5.

All DDR signals are terminated to VDDQ/2

6.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

7.

While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 kΩ 

resistor to V

TT

8.

While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kΩ resistor to 

V

SS

.

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for 
at least eight BCLKs for the processor to recognize the proper signal state. See 

 for the DC specifications. See 

 for additional timing 

requirements for entering and leaving the low power states.

Due to the voltage levels supported by other components in the Test Access Port (TAP) 
logic, it is recommended that the processor be first in the TAP chain and followed by 
any other components within the system. A translation buffer should be used to 
connect to the rest of the chain unless one of the other components is capable of 
accepting an input of the appropriate voltage. Two copies of each signal may be 
required with each driving a different voltage level. 

Single ended

CMOS Output

VTT_VID[4:2]

Single ended 

Analog Input

ISENSE

Single ended

Reset Input

RESET#

Single ended

Asynchronous Input

VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD

Power

VCC, VTTA, VTTD, VCCPLL, VDDQ

Asynchronous CMOS Output

PSI#

Sense Points

VCC_SENSE, VSS_SENSE

Other

SKTOCC#, DBR#

1.

Refer to 

 for signal descriptions.

2.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

• QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P], 

QPI_CLKTX_D[N/P]

• DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD
• BCLK_ITP_D[N/P]
• PECI
• BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD