Motorola IH5 User Manual
Memory Maps
http://www.motorola.com/computer/literature
2-5
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For detailed PCI memory maps, including suggested PREP-compatible
memory maps, refer to the MCPN750A CompactPCI Single Board
Computer Programmer’s Reference Guide (MCPN750A/PG).
memory maps, refer to the MCPN750A CompactPCI Single Board
Computer Programmer’s Reference Guide (MCPN750A/PG).
CompactPCI Memory Map
The MCPN750A uses the 21554 non-transparent PCI-to-PCI bridge to
interface between the local PCI bus and the CompactPCI bus. The 21554
is different from traditional PCI-to-PCI bridges in that it uses address
translation instead of a flat address map between primary and secondary
PCI buses. In the MCPN750A configuration, the primary bus is the
CompactPCI bus and the secondary bus is the MCPN750A local bus.
Downstream transactions are those that are initiated on the primary bus
and are forwarded to the secondary bus. Upstream transactions are those
initiated on the secondary bus and forwarded to the primary bus.
interface between the local PCI bus and the CompactPCI bus. The 21554
is different from traditional PCI-to-PCI bridges in that it uses address
translation instead of a flat address map between primary and secondary
PCI buses. In the MCPN750A configuration, the primary bus is the
CompactPCI bus and the secondary bus is the MCPN750A local bus.
Downstream transactions are those that are initiated on the primary bus
and are forwarded to the secondary bus. Upstream transactions are those
initiated on the secondary bus and forwarded to the primary bus.
Address Decoding with the 21554
The 21554 implements multiple base address registers on both the primary
and secondary interfaces that denote separate address ranges for both
downstream and upstream transactions. It also has base registers for access
to its Control and Status Register (CSR) space. Consequently, on the
primary interface (CompactPCI bus) the 21554 responds only to those
transactions which are in the address range defined by one of the base
address ranges. All other addresses are ignored. The same is true for
transactions on the secondary interface (local PCI bus).
and secondary interfaces that denote separate address ranges for both
downstream and upstream transactions. It also has base registers for access
to its Control and Status Register (CSR) space. Consequently, on the
primary interface (CompactPCI bus) the 21554 responds only to those
transactions which are in the address range defined by one of the base
address ranges. All other addresses are ignored. The same is true for
transactions on the secondary interface (local PCI bus).
The address ranges defined by the primary base address registers reside in
the primary or system address map. The address ranges defined by the
secondary base address registers reside in the secondary or local address
map. Each of these address maps is independent of each other. The 21554
provide address translation between these two address maps when
forwarding transactions upstream or downstream.
the primary or system address map. The address ranges defined by the
secondary base address registers reside in the secondary or local address
map. Each of these address maps is independent of each other. The 21554
provide address translation between these two address maps when
forwarding transactions upstream or downstream.
Recommendations for CompactPCI mapping, including suggested PREP-
compatible memory maps, can be found in the MCPN750A CompactPCI
Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG).
compatible memory maps, can be found in the MCPN750A CompactPCI
Single Board Computer Programmer’s Reference Guide
(MCPN750A/PG).