Compaq EV67 User Manual
Alpha 21264/EV67 Hardware Reference Manual
Cache and External Interfaces
4–49
Bcache Port
priate programming of the Bcache clock period and delay parameters to satisfy SSRAM
setup/hold requirements of the Bcache address latch, a Bcache write transaction pro-
ceeds through the Cbox as follows:
setup/hold requirements of the Bcache address latch, a Bcache write transaction pro-
ceeds through the Cbox as follows:
1. The Cbox transmits the index and write control signals during an Int_Adr_BcClk
edge.
2. The data is placed on Bcache data, tag, and tag status pins on the appropriate
Int_Data_BcClk edge from 0 to 7 Bcache bit-times later, based on the Cbox CSR
BC_LATE_WRITE_NUM[2:0]. The BC_LATE_WRITE_NUM[2:0] supports the
late-write SSRAM, which optimize Bcache data bus bandwidth by minimizing
bubbles between read and write transactions. For example, single-data late-write
SSRAMs would need this CSR programmed to a value of one, and dual-data late-
write SSRAMs would need this CSR programmed to a value of two.
BC_LATE_WRITE_NUM[2:0]. The BC_LATE_WRITE_NUM[2:0] supports the
late-write SSRAM, which optimize Bcache data bus bandwidth by minimizing
bubbles between read and write transactions. For example, single-data late-write
SSRAMs would need this CSR programmed to a value of one, and dual-data late-
write SSRAMs would need this CSR programmed to a value of two.
3. The difference between the data delivery (Int_Data_BcClk) and forwarded clocks
out provides the setup for the data at the Bcache data flip-flop.
4. For Bcache writes, the 21264/EV67 drivers are enabled on the GCLK BPHASE
preceding the start of a write transfer, and disabled on the succeeding GCLK
BPHASE at the end of a write transfer. Thus, the write data is enveloped by the
21264/EV67 drivers to guarantee that every data transfer has the same data-valid
window.
BPHASE at the end of a write transfer. Thus, the write data is enveloped by the
21264/EV67 drivers to guarantee that every data transfer has the same data-valid
window.
4.8.3.3 Bubbles on the Bcache Data Bus
When changing between read and write transactions on the bidirectional bus, it is often
necessary to introduce NOP cycles (bubbles) to allow the bus to settle and to drain the
Bcache read pipeline. The Cbox provides two CSRS, BC_RD_WR_BUBBLES[5:0]
and BC_WR_RD_BUBBLES[3:0], to help control the bubbles between read and write
transactions.
necessary to introduce NOP cycles (bubbles) to allow the bus to settle and to drain the
Bcache read pipeline. The Cbox provides two CSRS, BC_RD_WR_BUBBLES[5:0]
and BC_WR_RD_BUBBLES[3:0], to help control the bubbles between read and write
transactions.
The optimum parameters for these CSRs are determined by formulas that include the
following terms:
following terms:
Term
Description
bcfrm
Bcache frame clock.
•
In dual-data mode, bcfrm is twice the ratio.
•
In single-data mode, the value for bcfrm is determined by whether
the ratio is even or odd:
the ratio is even or odd:
–
When the ratio is even, bcfrm is equal to the ratio.
–
When the ratio is odd, bcfrm is twice the ratio.
For example, in single-data mode:
GCLK
The processor clock.
Ratio
Bcfrm
2
2
2.5
5