Compaq EV67 User Manual
5–28
Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Mbox IPRs
5.3.7 Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0,1
The Dstream translation buffer address space number registers (DTB_ASN0 and
DTB_ASN1) are write-only registers that should be written with the address space
number (ASN) of the current process. Figure 5–30 shows the Dstream translation buffer
address space number registers 0 and 1.
DTB_ASN1) are write-only registers that should be written with the address space
number (ASN) of the current process. Figure 5–30 shows the Dstream translation buffer
address space number registers 0 and 1.
Figure 5–30 Dstream Translation Buffer Address Space Number Registers 0 and 1
5.3.8 Memory Management Status Register – MM_STAT
The memory management status register (MM_STAT) is a read-only register.
When a Dstream TB miss or fault occurs, information about the error is latched in
MM_STAT. MM_STAT is not updated when a LD_VPTE gets a DTB miss instruction.
Figure 5–31 shows the memory management status register.
When a Dstream TB miss or fault occurs, information about the error is latched in
MM_STAT. MM_STAT is not updated when a LD_VPTE gets a DTB miss instruction.
Figure 5–31 shows the memory management status register.
Figure 5–31 Memory Management Status Register
Table 5–18 describes the memory management status register fields.
Table 5–18 Memory Management Status Register Fields Description
Name
Extent
Type
Description
Reserved
[63:11]
—
—
DC_TAG_PERR
[10]
RO
This bit is set when a Dcache tag parity error occurred during the
initial tag probe of a load or store instruction. The error created a
synchronous fault to the D_FAULT PALcode entry point and is
correctable. The virtual address associated with the error is avail-
able in the VA register.
initial tag probe of a load or store instruction. The error created a
synchronous fault to the D_FAULT PALcode entry point and is
correctable. The virtual address associated with the error is avail-
able in the VA register.
OPCODE[5:0]
[9:4]
RO
Opcode of the instruction that caused the error.
HW_LD is displayed as 3 and HW_ST is displayed as 7.
HW_LD is displayed as 3 and HW_ST is displayed as 7.
FOW
[3]
RO
This bit is set when a fault-on-write error occurs during a write
transaction and PTE[FOW] was set.
transaction and PTE[FOW] was set.
63
56 55
0
ASN[7:0]
LK99-0038A
63
9
4 3 2
11
1
10
0
DC_TAG_PERR
OPCODE[5:0]
FOW
FOR
ACV
WR
LK99-0039A