Compaq EV67 User Manual

Internal Processor Registers

Figure 5–35 shows the Cbox data register.

Table 5–22 describes the Cbox data register fields.

Figure 5–36 shows the Cbox shift register.

Table 5–23 describes the Cbox shift register fields.

The WRITE_ONCE chain order is contained in Table 5–24. In the table:

Many CSRs are duplicated for ease of hardware implementation. These CSRs  are 
indicated in italics. They must be written with values that are identical to the values 
written to the original CSRs.

Reserved

[63:6]

—

—

C_DATA[5:0]

[5:0]

RW

Cbox data register. A HW_MTPR instruction to this register causes six 
bits of data to be placed into a serial shift register. When the 
HW_MTPR instruction is retired, the data is shifted into the Cbox. After 
the Cbox shift register has been accessed, performing a HW_MFPR 
instruction to this register will return six bits of data.

Reserved

[63:1]

—

—

C_SHIFT

[0]

W1

Writing a 1 to this register bit causes six bits of Cbox IPR data to shift into 
the Cbox data register. Software can then use a HW_MFPR read operation 
to the Cbox data register to read the six bits of data.

63

6 5

0

C_DATA[5:0]

LK99-0043A

63

1 0

C_SHIFT

LK99-0044A