Compaq EV67 User Manual

Privileged Architecture Library Code

This section shows the expected PALcode flows for DTB miss and ITB miss. Familiar-
ity with 21264/EV67 IPRs is assumed.

Figure 6–5 shows single-miss DTB instructions flow. 

Figure 6–5 shows single-miss DTB instructions flow.  

 

hw_mfprp23, EV6__EXC_ADDR

; (0L) get exception address

 

hw_mfprp4, EV6__VA_FORM

; (4-7,1L) get vpte address

 

hw_mfprp5, EV6__MM_STAT

; (0L) get miss info

 

hw_mfpr p7, EV6__EXC_SUM

; (0L) get exc_sum for ra

 

 

hw_mfpr p6, EV6__VA

; (4-7,1L) get original va

 

bic p7, #1, p7

; clear double miss flag

 

xor p4, p6, p4

; interlock p4 and p6

 

xor p4, p6, p4

; restore p4

 

 trap__dtbm_single_vpte:

 

hw_ldq/v p4, (p4)

; (1L) get vpte

 

blt p_misc, trap__d1to1

; (xU) <63>=1 => 1-to-1

 

blbcp4, trap__invalid_dpte

; (xU) invalid => branch

 

 

and p4, #^x80, p7

; isolate mb bit

 

xor p7, #^x80, p7

; flip mb bit

 

 ALIGN_FETCH_BLOCK 

<^x47FF041F>

 

 

PVC_VIOLATE <2>

; ignore scoreboard violation

 

hw_mtprp6, EV6__DTB_TAG0

; (2&6,0L) write tag0

 

hw_mtpr p6, EV6__DTB_TAG1

; (1&5,1L) write tag1

MCHK

Interrupt

500

Machine check.

ITB_MISS

Fault

580

Istream TB miss.

ARITH

Synch. Trap 600

Arithmetic exception or update to FPCR.

INTERRUPT

Interrupt

680

Interrupts: hardware, software, and AST.

MT_FPCR

Synch. Trap 700

Invoked when a MT_FPCR instruction is issued.

RESET/WAKEUP

Interrupt

780

Chip reset or wake-up from sleep mode.