Compaq EV67 User Manual

Privileged Architecture Library Code

The legal range for PCTR0 when writing the IPR is 0

:

(2**20-16).

The legal range for PCTR1 when writing the IPR is 0

:

(2**20-4).

1. Setup

The following IPRs need to be set up by PALcode instructions.

2. Count

If PCTR0 and PCTR1 are enabled, will increment according to modes selected by 
SL0 and SL1.

3. Overflow

If PCEN[1:0] is enabled, PC[1:0] is set when PCTR0 or PCTR1 overflows.

4. Hardware interrrupt

When PC[1:0] is set, the PALcode interrupt routine is entered. Interrupt is acknowl-
edged and PALcode generates an interrupt to the operating system performance 
monitoring utility.

5. Operating system interrupt handler

The handler should read the IPR PCTR_CTL, as shown in Table 6–10, to note 
which counter overflowed in the handler's data structures. The handler may read the 
counter to see how many events have happened since the overflow. 

The handler may also choose to write the counters to control the frequency of inter-
rupts.

IER_CM

PCEN[1:0]

Enable Interrupts.

PCTX

PPCE

Enable Process Performance Counting or use I_CTL[SPCE].

PCTR_CTL

SL0

Selects Aggregate or ProfileMe mode; set to 0 for Aggregate mode.

SL1

Selects PCTR0 and PCTR1 counting modes. See Table 6–11 for more infor-
mation. 

PCTR0[19:0]

Set counter 0 starting value [0:(2**20-16)]. See Section 6.10.1 for setup 
precautions.

PCTR1[19:0]

Set counter 1 starting value [0:(2**20-4)]. See Section 6.10.1 for setup pre-
cautions.

I_CTL

SPCE

Enable System Performance Counting or use PCTX[PPCE].

PCT0_EN

Enable performance counter 0.

PCT1_EN

Enable performance counter 1.

PCTR_CTL

PCTR0[19:0]

Counter #0 value

PCTR1[19:0]

Counter #1 value