Compaq EV67 User Manual

Initialization and Configuration

In addition, as power is being ramped, Reset_L must be asserted — this allows the 
21264/EV67 to reset internal state.  Once the target voltage levels are attained, systems 
should assert DCOK_H.  This indicates to the 21264/EV67 that internal logic functions 
can be evaluated correctly and that the power-up sequence should be continued. Prior to 
DCOK_H being asserted, the logic internal to the 21264/EV67 is being reset and the 
internal clock network is running (either clocked by the PLL VCO, which is at a nomi-
nal speed, or by ClkIn_H, if the PLL is bypassed). 

The reset state machine is in state WAIT_SETTLE. 

When DCOK_H is asserted, the 21264/EV67 samples several pins and latches in some 
initialization state, including the value of the PLL Y

div

 divisor,  which specifies the 

ratio of the system clock to the internal clock (see Section 7.11.2.3), and enables the 
charge pump on the phase-locked loop.

Initially, during power-up reset, state 
is not defined. If not during power-
up, preserves previous state. Then, 
after the clock forward reset period 
(as the external clocks start), signal 
driven to NZNOP until the reset 
state machine enters RUN, when it 
is driven to NOP.

NA (input)

Tristated

NA (input)

Tristated

NA
(I_DC_REF)

Tristated

NA (input)

NA (input)

NA (input)

NA 
(I_DC_REF)

NA (input)

Must be deasserted until dc voltage 
reaches proper operating level. 

NA (input)

NA (input)

NA (input)

NA (input)

Unspecified

Tristated

Tristated

NA (input)

NA (input)

Tristated

NA (input)