Compaq EV67 User Manual
7–12
Initialization and Configuration
Alpha 21264/EV67 Hardware Reference Manual
Array Initialization
The 21264/EV67 waits until Reset_L is deasserted before transitioning from the
WAIT_RESET state. The 21264/EV67 ramps up the PLL until the state machine enters
the WAIT_ClkFwdRst0 state. Note that the system must assert ClkFwdRst_H before
the state machine enters the WAIT_ClkFwdRst0 state. Then, similarly to the other
flows, SromOE_L is asserted and the system waits for the deassertion of
ClkFwdRst_H.
WAIT_RESET state. The 21264/EV67 ramps up the PLL until the state machine enters
the WAIT_ClkFwdRst0 state. Note that the system must assert ClkFwdRst_H before
the state machine enters the WAIT_ClkFwdRst0 state. Then, similarly to the other
flows, SromOE_L is asserted and the system waits for the deassertion of
ClkFwdRst_H.
On the deassertion of ClkFwdRst_H, the 21264/EV67 performs BiST and the SROM
loading procedure.
loading procedure.
After BiST and SROM loading have completed, SromOE_L deasserts and the 21264/
EV67 waits for ClkFwdRst_H to deassert before starting the external clocks and, like
the other flows, waits for 264 cycles before starting instructions.
EV67 waits for ClkFwdRst_H to deassert before starting the external clocks and, like
the other flows, waits for 264 cycles before starting instructions.
7.5 Array Initialization
The following arrays are initialized by BiST:
•
Icache and Icache tag
•
Dcache, Dcache tag, and Duplicate Dcache tag
•
Branch history table
The external second-level cache (Bcache) is disabled by Reset_L.
The Bcache must be initialized by PALcode before it is enabled.
7.6 Initialization Mode Processing
The initialization mode allows the 21264/EV67 to generate and manipulate cache
blocks before the system interface has been initialized. Within the 21264/EV67, the
Cbox configuration registers are divided into the WRITE_ONCE and the
WRITE_MANY shift register chains (see Sections 5.4.3 and 5.4.4). The
WRITE_ONCE chain is loaded from the SROM during reset processing, and contains
information such as the clock forwarding setup values. The WRITE_MANY chain can
be written many times using MTPR instructions.
blocks before the system interface has been initialized. Within the 21264/EV67, the
Cbox configuration registers are divided into the WRITE_ONCE and the
WRITE_MANY shift register chains (see Sections 5.4.3 and 5.4.4). The
WRITE_ONCE chain is loaded from the SROM during reset processing, and contains
information such as the clock forwarding setup values. The WRITE_MANY chain can
be written many times using MTPR instructions.
The WRITE_MANY chain contains the following CSRs that are important to initializa-
tion mode, which must be set to the values in Table 7–9 to initialize the Bcache.
tion mode, which must be set to the values in Table 7–9 to initialize the Bcache.
Table 7–9 WRITE_MANY Chain CSR Values for Bcache Initialization
WRITE_MANY Chain CSRs
Required Value at Initialization Mode
BC_ENABLE
1
The duplicate bits for BC_ENABLE in [14:12] must
be 0 during initialization mode.
The duplicate bits for BC_ENABLE in [14:12] must
be 0 during initialization mode.
BC_SIZE[3:0]
The exact size or maximum size of the Bcache.
INVAL_TO_DIRTY_ENABLE[1:0]
1
SET_DIRTY_ENABLE[2:0]
0
INIT_MODE
1