Compaq EV67 User Manual

Electrical Data

This section contains the dc characteristics for the 21264/EV67. The 21264/EV67 pins 
can be divided into 10 distinct electrical signal types. The mapping between these sig-
nal types and the package pins is shown in Chapter 3. Table 9–2 shows the signal types.

Tables 9–3 through 9–12 show the  dc switching characteristics of each signal type. 
Also, the following notes apply to Tables 9–3 to 9–12.

1. The differential voltage, Vdiff, is the absolute difference between the differential 

input pins.

2. Delta V

BIAS

  is defined as the open-circuit differential voltage on the appropriate 

differential pairs. Test condition for these inputs are to let the input network self 
bias and measure the open circuit voltage. The test load must be 

≥

 1M ohm. In nor-

mal operation, these inputs are coupled with a 680-pF capacitor.

3. Functional operation of the 21264/EV67 with less than all VDD and VSS pins con-

nected is not implied.

4. The test load is a 50-ohm resistor to VDD/2. The resistor can be connected to the 

21264/EV67 pin by a 50-ohm transmission line of any length.

5. DC test conditions set the minimum swing required. These dc limits set the trip 

point precision.

6. Input pin capacitance values include 2.0 pF added for package capacitance.

I_DC_POWER

Supply voltage pins (VDD/PLL_VDD)

I_DC_REF

Input dc reference pin

I_DA

Input differential amplifier receiver

I_DA_CLK

Input differential amplifier clock receiver

O_OD

Open-drain output driver

O_OD_TP

Open-drain driver for test pins

O_PP

Push-pull output driver

O_PP_CLK

Push-pull output clock driver

B_DA_OD

Bidirectional differential amplifier receiver — open-drain

B_DA_PP

Bidirectional differential amplifier receiver — push-pull