Compaq EV67 User Manual
Alpha 21264/EV67 Hardware Reference Manual
PALcode Restrictions and Guidelines
D–1
D
PALcode Restrictions and Guidelines
D.1 Restriction 1 : Reset Sequence Required by Retire Logic and
Mapper
For convenience of implementation, the Ibox retire logic done status bits are not initial-
ized during reset. Instead, as shown in the example below, the first batch of valid
instructions sweeps through inum-space and initializes these bits. The 80 status bits
(one for each inflight instruction) must be marked not done by the first 80 instructions
mapped after reset, and later marked done when those instructions are retired. There-
fore, the first 20 fetch blocks must contain four valid instructions each, and must not
contain any retire logic NOP instructions.
ized during reset. Instead, as shown in the example below, the first batch of valid
instructions sweeps through inum-space and initializes these bits. The 80 status bits
(one for each inflight instruction) must be marked not done by the first 80 instructions
mapped after reset, and later marked done when those instructions are retired. There-
fore, the first 20 fetch blocks must contain four valid instructions each, and must not
contain any retire logic NOP instructions.
reset:
** (1) Initialize 80 retirator "done" status bits and
** the integer and floating mapper destinations.
** (2) Do A MTPR ITB_IA, which turns on the mapper source
** enables.
** (3) Create a map stall to complete the ITB_IA.
**
** State after execution of this code:
**
retirator initialized
**
destinations mapped
**
source mapping enabled
**
itb flushed
**
** The PALcode need not assume the following since the SROM is not
** required to do these:
**
dtb flushed
**
dtb_asn0 0
**
dtb_asn1
0
**
dtb_alt_mode
0
*/
/*
** Initialize retirator and destination map, doing 80 retires.
*/
addq r31,r31,r0
/* initialize Int. Reg. 0*/
addq r31,r31,r1
/* initialize Int. Reg. 1*/
addt f31,f31,f0
/* initialize F.P. Reg. 0*/
mult f31,f31,f1
/* initialize F.P. Reg. 1*/
addq r31,r31,r2
/* initialize Int. Reg. 2*/
addq r31,r31,r3
/* initialize Int. Reg. 3*/