Compaq EV67 User Manual

Dcache

described

,

duplicate tag parity errors

,

duplicate tags with

,

error case summary for

,

fill from Bcache error

,

fill from memory errors

,

initialized by BiST

,

pipelined

,

single-bit correctable ECC error

,

store second error

,

tag parity errors

,

victim extracts

,

Dcache data single-bit correctable ECC errors

,

Dcache tag, initialized by BiST

,

DCOK_H signal pin

,

power-on reset flow

,

DCVIC_THRESHOLD Cbox CSR, defined

,

DFAULT fault

,

Differential 21264/EV67 clocks

,

Differential reference clocks

,

Dirty cache block state

,

Dirty/Shared cache block state

,

Do not care convention

,

Double-bit fill errors

,

DOWN1 reset machine state

,

DOWN2 reset machine state

,

DOWN3 reset machine state

,

Dstream translation buffer

,

DSTREAM_BC_DBL error status in C_STAT

,

DSTREAM_BC_ERR error status in C_STAT

,

DSTREAM_DC_ERR error status in C_STAT

,

DSTREAM_MEM_DBL error status in C_STAT

,

DSTREAM_MEM_ERR error status in C_STAT

,

DTB entries, writing multiple in same PAL flow

,

DTB fill

,

DTB, pipeline abort delay with

,

DTB_ALTMODE alternate processor mode register

,

at power-on reset state

,

DTB_ASN0 address space number register 0

at power-on reset state

,

DTB_ASN0 address space number registers 0

,

DTB_ASN1 address space number register 1

,

at power-on reset state

,

DTB_IA invalidate-all process register

,

at power-on reset state

,

DTB_IAP invalidate-all (ASM=0) process register

,

at power-on reset state

,

DTB_IS0 invalidate single (array 0) register

,

at power-on reset state

,

DTB_IS1 invalidate single (array 1) register

,

at power-on reset state

,

DTB_PTE0 array write 0 register

at power-on reset state

,

MTPR to

,

DTB_PTE0 array write register 0

,

DTB_PTE1 array write 1 register

,

at power-on reset state

,

MTPR to

,

DTB_TAG0 array write 0 register

,

at power-on reset state

,

MTPR to

,

DTB_TAG1 array write 1 register

,

at power-on reset state

,

MTPR to

,

DTBM_DOUBLE_3 fault

,

DTBM_DOUBLE_4 fault

,

DTBM_SINGLE fault

,

Dual-data rate SSRAM pin assignments

,

DUP_TAG_ENABLE Cbox CSR, defined

,

Duplicate Dcache tag array

,

Duplicate Dcache, initialized by BiST

,

Duplicate tag stores, Bcache

,

Ebox

cycle counter control register CC_CTL

cycle counter register CC

,

described

,

executed in pipeline

,

internal processor registers

,

slotting

,

subclusters

,

virtual address control register VA_CTL

,

virtual address format register VA_FORM

,

virtual address register

,

ECB instruction, external interface reference

,