Compaq EV67 User Manual

MB, 21264/EV67 command

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MB_CNT Cbox CSR, operation

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MBDone, SysDc command

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Mbox

Dcache control register DC_CTL

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Dcache status register DC_STAT

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described

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Dstream translation buffer

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DTB address space number registers 0 and 1 

DTB_ASNx

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DTB alternate processor mode register 

DTB_ALTMODE

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DTB invalidate-all (ASM=0) process register 

DTB_IAP

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DTB invalidate-all process register DTB_IA

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DTB invalidate-single registers 0 and 1 

DTB_ISx

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DTB PTE array write registers 0 and 1 

DTB_PTEx

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DTB tag array write registers 0 and 1 

DTB_TAGx

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internal processor registers

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load queue

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Mbox control register M_CTL

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memory management status register 

MM_STAT

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miss address file

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order traps

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pipeline abort delay with order trap

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pipeline abort delays

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store queue

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MBOX_BC_PRB_STALL Cbox CSR, defined

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MCHK interrupt

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Mechanical specifications

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Memory

error case summary for

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filling Dcache errors

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filling Icache errors

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Memory address space

load instructions with

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merging rules

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store instructions with

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Memory barrier instructions

translation to external interface

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Memory barriers

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MF_FPCR instruction

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Microarchitecture

summarized

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MiscVref signal pin

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Miss address file

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I/O address space loads

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memory address space loads

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memory address space stores

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MM_STAT memory management status register

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at power-on reset state

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MT_FPCR instruction

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MT_FPCR synchronous trap

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NoConnect pin type

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Nonexistent memory

processing

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NOP, 21264/EV67 command

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Note convention

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Numbering convention

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NZNOP, 21264/EV67 command

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O_OD pin type

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values for

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O_OD_TP pin type

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values for

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O_PP pin type

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values for

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O_PP_CLK pin type

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values for

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OPCDEC fault

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Opcodes

IEEE floating-point

,

independent floating-point

,

reserved for Compaq

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reserved for PALcode

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summary of

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VAX floating-point

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Operating temperature

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Packaging

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Paired instruction fetch order

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PAL_BASE register

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after fault reset

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after warm reset

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at power-on reset state

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through sleep mode

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