Compaq EV67 User Manual
2–8
Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
21264/EV67 Microarchitecture
The FQ arbiters pick between simultaneous requesters of a pipeline based on the age of
the request—older requests are given priority over newer requests. Floating-point store
instructions and FTOIx instructions in even-numbered queue entries arbitrate for one
store port. Floating-point store instructions and FTOIx instructions in odd-numbered
queue entries arbitrate for the second store port.
the request—older requests are given priority over newer requests. Floating-point store
instructions and FTOIx instructions in even-numbered queue entries arbitrate for one
store port. Floating-point store instructions and FTOIx instructions in odd-numbered
queue entries arbitrate for the second store port.
Floating-point store instructions and FTOIx instructions are queued in both the integer
and floating-point queues. They wait in the floating-point queue until their operand reg-
ister values are available. They subsequently request service from the store arbiter.
Upon being issued from the floating-point queue, they signal the corresponding entry in
the integer queue to request service. Upon being issued from the integer queue, the
operation is completed.
and floating-point queues. They wait in the floating-point queue until their operand reg-
ister values are available. They subsequently request service from the store arbiter.
Upon being issued from the floating-point queue, they signal the corresponding entry in
the integer queue to request service. Upon being issued from the integer queue, the
operation is completed.
2.1.1.8 Exception and Interrupt Logic
There are two types of exceptions: faults and synchronous traps. Arithmetic exceptions
are precise and are reported as synchronous traps.
are precise and are reported as synchronous traps.
The four sources of interrupts are listed as follows:
•
Level-sensitive hardware interrupts sourced by the IRQ_H[5:0] pins
•
Edge-sensitive hardware interrupts generated by the serial line receive pin,
performance counter overflows, and hardware corrected read errors
performance counter overflows, and hardware corrected read errors
•
Software interrupts sourced by the software interrupt request (SIRR) register
•
Asynchronous system traps (ASTs)
Interrupt sources can be individually masked. In addition, AST interrupts are qualified
by the current processor mode.
by the current processor mode.
2.1.1.9 Retire Logic
The Ibox fetches instructions in program order, executes them out of order, and then
retires them in order. The Ibox retire logic maintains the architectural state of the
machine by retiring an instruction only if all previous instructions have executed with-
out generating exceptions or branch mispredictions. Retiring an instruction commits the
machine to any changes the instruction may have made to the software-visible state.
The three software-visible states are listed as follows:
retires them in order. The Ibox retire logic maintains the architectural state of the
machine by retiring an instruction only if all previous instructions have executed with-
out generating exceptions or branch mispredictions. Retiring an instruction commits the
machine to any changes the instruction may have made to the software-visible state.
The three software-visible states are listed as follows:
•
Integer and floating-point registers
•
Memory
•
Internal processor registers (including control/status registers and translation
buffers)
buffers)
The retire logic can sustain a maximum retire rate of eight instructions per cycle, and
can retire up to as many as 11 instructions in a single cycle.
can retire up to as many as 11 instructions in a single cycle.
2.1.2 Integer Execution Unit
The integer execution unit (Ebox) is a 4-path integer execution unit that is implemented
as two functional-unit “clusters” labeled 0 and 1. Each cluster contains a copy of an 80-
entry, physical-register file and two “subclusters”, named upper (U) and lower (L). Fig-
ure 2–6 shows the integer execution unit. In the figure, iop_wr is the cross-cluster bus
for moving integer result values between clusters.
as two functional-unit “clusters” labeled 0 and 1. Each cluster contains a copy of an 80-
entry, physical-register file and two “subclusters”, named upper (U) and lower (L). Fig-
ure 2–6 shows the integer execution unit. In the figure, iop_wr is the cross-cluster bus
for moving integer result values between clusters.