Compaq EV67 User Manual
Alpha 21264/EV67 Hardware Reference Manual
Internal Architecture
2–33
I/O Write Buffer and the WMB Instruction
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RdBlkSpec (valid), RdBlkModSpec (valid), RdBlkSpecI (valid)
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RdBlkVic, RdBlkModVic, RdBlkVicI
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CleanToDirty, SharedToDirty, STChangeToDirty, InvalToDirty
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FetchBlk, FetchBlkSpec (valid), Evict
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RdByte, RdLw, RdQw, WrByte, WrLW, WrQW
The counter is decremented with the C (commit) bit in the Probe and SysDc commands
(see Section 4.7.7). Systems can assert the C bit in the SysDc fill response to the com-
mands that originally incremented the counter, or attached to the last probe seen by that
command when it reached the system serialization point. If the number of uncommitted
transactions reaches 15 (saturating the counter), the Cbox will stall MAF and IOWB
processing until at least one of the pending transactions has been committed. Probe pro-
cessing is not interrupted by the state of this counter.
(see Section 4.7.7). Systems can assert the C bit in the SysDc fill response to the com-
mands that originally incremented the counter, or attached to the last probe seen by that
command when it reached the system serialization point. If the number of uncommitted
transactions reaches 15 (saturating the counter), the Cbox will stall MAF and IOWB
processing until at least one of the pending transactions has been committed. Probe pro-
cessing is not interrupted by the state of this counter.
2.12.1.1 MB Instruction Processing
When an MB instruction is fetched in the predicted instruction execution path, it stalls
in the map stage of the pipeline. This also stalls all instructions after the MB, and con-
trol of instruction flow is based upon the value in Cbox CSR SYSBUS_MB_ENABLE
as follows:
in the map stage of the pipeline. This also stalls all instructions after the MB, and con-
trol of instruction flow is based upon the value in Cbox CSR SYSBUS_MB_ENABLE
as follows:
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If Cbox CSR SYSBUS_MB_ENABLE is clear, the Cbox waits until the IQ is
empty and then performs the following actions:
empty and then performs the following actions:
a.
Sends all pending MAF and IOWB entries to the system port.
b. Monitors Cbox CSR MB_CNT[3:0], a 4-bit counter of outstanding committed
events. When the counter decrements from one to zero, the Cbox marks the
youngest probe queue entry.
youngest probe queue entry.
c.
Waits until the MAF contains no more Dstream references and the SQ, LQ, and
IOWB are empty.
IOWB are empty.
When all of the above have occurred and a probe response has been sent to the sys-
tem for the marked probe queue entry, instruction execution continues with the
instruction after the MB.
tem for the marked probe queue entry, instruction execution continues with the
instruction after the MB.
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If Cbox CSR SYSBUS_MB_ENABLE is set, the Cbox waits until the IQ is empty
and then performs the following actions:
and then performs the following actions:
a.
Sends all pending MAF and IOWB entries to the system port
b. Sends the MB command to the system port
c.
Waits until the MB command is acknowledged, then marks the youngest entry
in the probe queue
in the probe queue
d. Waits until the MAF contains no more Dstream references and the SQ, LQ, and
IOWB are empty
When all of the above have occurred and a probe response has been sent to the sys-
tem for the marked probe queue entry, instruction execution continues with the
instruction after the MB.
tem for the marked probe queue entry, instruction execution continues with the
instruction after the MB.