Compaq EV67 User Manual

Hardware Interface

The 21264/EV67 package has 587 pins aligned in a pin grid array (PGA) design.  There 
are 380 functional signal pins, 1 dedicated 3.3-V pin for the PLL, 112 ground VSS pins, 
and 94 VDD pins. Table 3–4 lists the  signal pins and their corresponding pin grid array 
(PGA) locations in alphabetical order for the signal type. Table 3–5 lists the pin grid 
array locations in alphabetical order

I_DA

1

System reset. This signal protects the 21264/EV67 from dam-
age during initial power-up. It must be asserted until 
DCOK_H is asserted. After that, it is deasserted and the 
21264/EV67 begins its reset sequence.

O_OD_TP

1

Serial ROM clock.

I_DA

1

Serial ROM data.

O_OD_TP

1

Serial ROM enable.

I_DA

1

IEEE 1149.1 test clock.

I_DA

1

IEEE 1149.1 test data-in signal.

O_OD_TP

1

IEEE 1149.1 test data-out signal.

O_OD_TP

1

Test status pin.

I_DA

1

IEEE 1149.1 test mode select signal.

I_DA

1

IEEE 1149.1 test access port (TAP) reset signal.

B30

D30

C31

H28

G29

A33

E31

D32

B34

A35

B36

H30

C35

E33

B28

E27

A29

G27

C29

F28

F2

AB4

AW1

BD10

E45

AC45

AT44

BB36

AT2

BC11

M38

AB42

AU43

BC37

M8

AA3

B10

D10

L3

D42

D44

H40

H42

G45

L43