Compaq EV67 User Manual

Cache and External Interfaces

This chapter describes the 21264/EV67 cache and external interface, which includes the 
second-level cache (Bcache) interface and the system interface. It also describes locks, 
interrupt signals, and ECC/parity generation. It is organized as follows: 

Introduction to the external interfaces

Physical address considerations

Bcache structure

Victim data buffer

Cache coherency

Lock mechanism

System port

Bcache port

Interrupts

Chapter 3 lists and defines all 21264/EV67 hardware interface signal  pins. Chapter 9 
describes the 21264/EV67 hardware interface electrical  requirements.

A 21264/EV67-based system can be divided into three major sections: 

21264/EV67 microprocessor

Second-level Bcache

System interface logic 

–

Optional duplicate tag store

–

Optional lock register

–

Optional victim buffers

The 21264/EV67 external interface is flexible and mandates few design rules, allowing 
a wide range of prospective systems. The external interface is composed of the Bcache 
interface and the system interface.

Input clocks must have the same frequency as their corresponding output clock. For 
example, the frequency of SysAddInClk_L  must be the same as 
SysAddOutClk_L.