Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual

Product codes

AT80580PJ0736MG

Datasheet

Electrical Specifications

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in

3.7

FSB Signal Groups

The FSB signals have been combined into groups by buffer type in the following

sections. AGTL+ input signals have differential input buffers that use GTLREF as a

reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input

group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers

to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source-synchronous data bus, two sets of timing

parameters need to be specified. One set is for common clock signals, which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second

set is for the source-synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle.

identifies which signals are common clock, source synchronous,

and asynchronous.

Table 4.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1]

BSEL[0]

BCLK Frequency

266 MHz

RESERVED