Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual

Datasheet

35

NOTES:
1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

V

IL

 

is defined as the maximum voltage level at a receiving agent that will be interpreted as 

a logical low value.

3.

V

IH

 is defined as the minimum voltage level at a receiving agent that will be interpreted as 

a logical high value.

4.

V

IH

 and V

OH

 may experience excursions above V

CCP

. However, input signal drivers must 

comply with the signal quality specifications.

5.

This is the pulldown driver resistance. Refer to processor I/O Buffer Models for I/V 
characteristics. Measured at 0.31*V

CCP

. R

ON 

(min) = 0.418*R

TT

, R

ON 

(typ) = 0.455*R

TT

, 

R

ON 

(max) = 0.527*R

TT

. R

TT

 typical value of 55 Ω is used for R

ON

 typ/min/max 

calculations.

6.

GTLREF/GTLREF_2 should be generated from V

CCP

 with a 1% tolerance resistor divider. 

The V

CCP

 referred to in these specifications is the instantaneous V

CCP

.

7.

R

TT

 is the on-die termination resistance measured at V

OL

 of the AGTL+ output driver. 

Measured at 0.31*V

CCP

. R

TT 

is connected to V

CCP

 on die. Refer to processor I/O buffer 

models for I/V characteristics.

8.

Specified with on-die R

TT 

and R

ON 

turned off. Vin between 0 and V

CCP

.

9.

Cpad includes die capacitance only. No package parasitics are included.

10.

This is the external resistor on the comp pins.

11.

On-die termination resistance, measured at 0.33*V

CCP

.

12.

Applies to Signals A[35:3].

13.

Applies to Signals D[63:0].

14.

Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#, 
BPM[3:0], BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#, 
DSTBP[3:0] and DSTBN[3:0]#.

R

TT/A

Termination Resistance 
Address

45

50

55

Ω

 7, 12

R

TT/D

Termination Resistance 
Data

45

50

55

Ω

 7, 13

R

TT/Cntrl

Termination Resistance 
Control

45

50

55

Ω

 7, 14

R

ON/A

Buffer On Resistance 
Address

8.25

8.33

12.25

Ω

5, 12

R

ON/D

Buffer On Resistance 
Data

8.25

8.33

12.25

Ω

5, 13

R

ON/Cntrl

Buffer On Resistance 
Control

8.25

8.33

12.25

Ω

5, 14

I

LI

Input Leakage Current

—

—

± 100

µA

8

Cpad

Pad Capacitance

1.80

2.30

2.75

pF

9