Intel Core 2 Quad Q9505 AT80580PJ0736MG User Manual
Product codes
AT80580PJ0736MG
Datasheet
7
Introduction
1
Introduction
The Intel® Core
TM
2 Extreme quad-core processor and Intel® Core
TM
2 quad processor
on 45-nanometer process technology for platforms based on Mobile Intel® 4 Series
Express Chipset Family is the first low-power, mobile quad-core processor based on the
Intel® Core™ microarchitecture.
In this document, the Intel Core
2 Extreme quad-core processor and Intel Core
2 quad
processor are referred to as the processor or quad-core processor and the Mobile Intel
4 Series Express Chipset is referred to as the (G)MCH.
Key features of the processor include:
• Quad-core mobile processor for mobile with enhanced performance
• Supports Intel® architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache in each
• Supports Intel® architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache in each
core
• 12-MB second-level shared cache with Advanced Transfer Cache architecture
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),
supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets
• Processors are offered at 1066-MHz source-synchronous front side bus (FSB)
• Advanced power management features including Enhanced Intel SpeedStep®
• Advanced power management features including Enhanced Intel SpeedStep®
Technology
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Supports Enhanced Intel® Virtualization Technology
• Supports PSI2 functionality
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for core to bus ratio
• Intel® 64 architecture
• Supports Enhanced Intel® Virtualization Technology
• Supports PSI2 functionality
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for core to bus ratio
1.1
Terminology
Term
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Front Side Bus
(FSB)
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
known as the chipset components).
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
signaling technology on some Intel processors.