Fujitsu FR20 User Manual
77
3.12.10
Gear Function
The gear function supplies to thin out the clock. There are two types of independent
circuits (for the CPU and for peripherals), and data can be transmitted and received
between the CPU and peripherals even with different gear ratios. Furthermore, whether
to use a clock with the same cycle as the clock from the oscillation circuit or a clock via
the 1/2 division circuit can be specified as the original clock selection.
circuits (for the CPU and for peripherals), and data can be transmitted and received
between the CPU and peripherals even with different gear ratios. Furthermore, whether
to use a clock with the same cycle as the clock from the oscillation circuit or a clock via
the 1/2 division circuit can be specified as the original clock selection.
■
Block Diagram of Gear Control Section
Figure 3.12-12 Block diagram of gear control section
■
Setting of Gear Function
The requested gear ratio can be set by setting the CCK1, 0 bit of the gear control register (GCR) to the
requested value under the CPU clock control, or by setting the PCK1, 0 bit of the same register to the
requested value under the peripheral clock control.
[example]
LDI:32 #GCR,R2
LDI:8 #11111100b,R1
; CCK=11, PCK=11, CHC=0
STB R1,@R2
; CPU clock=1/8f, Peripheral clock=1/8f, f=direct
LDI:8 #01111000b,R1
; CCK=01, PCK=10, CHC=0
STB R1,@R2
; CPU clock=1/2f, Peripheral clock=1/4f, f=direct
LDI:8 #00111000b,R1
; CCK=00, PCK=10, CHC=0
STB R1,@R2
; CPU clock=f, Peripheral clock=1/4f, f=direct
PLL
1/ 2
(1 multiplication)
X0
X1
X1
Selection
circuit
Oscillation
circuit
CCK
PCK
CHC
Inaternal clock generation circuit selection circuit
Internal peripheral
clock
Internal bus
clock
CPU clock
Internal bus
Gear interval indication
signal for CPU
signal for CPU
Gear interval
generation circuit
for CPU clock
generation circuit
for CPU clock
Gear interval
generation circuit
for peripheral clock
generation circuit
for peripheral clock
Gear interval indication
signal for peripheral
signal for peripheral