Planar EL640.480-AM User Manual
EL640.480-AM Operations Manual (020-0351-00C)
11
S (FRAME)
CP1 (LINE)
UD0 to UD3
LD0 to LD3
LD0 to LD3
CP2 (SHIFT)
tSU
tHOLD
tF
tR
tS21
tS12
tF
tR
tSU
tHOLD
tS3
tCLK
tCL
tCH
Figure 4. Setup and Hold Timing Diagram.
Table 5. Setup and Hold Timing.
Symbol Name
Min.
Max
Unit
tS21
CP1 allowance from CP2
0
ns
tS12
CP2 allowance from CP1
200
ns
tS3
CP1 allowance to CP2
50
ns
tSU Setup
time
50
ns
tHOLD Hold
time
40
ns
tR Rise
time
30
ns
tF Fall
time
30
ns
tCLK
CP2 clock cycle
154
ns
tCL
CP2 clock low time
60
ns
tCH
CP2 clock high time
60
ns
Input signals UD0 through UD3 contain the video data for the upper screen
and signals LD0 through LD3 contain the data for the lower screen. For
example, four pixels (UD3:1,1–UD0:1,1) are sent to row 1 at the same time as
four pixels (LD0:1,1–LD3:1,1) are sent to row 241. This results in eight pixels
sent on each cycle of video clock CP2. Pixel information is supplied from left to
right and from top to bottom. Video data for one row is latched on the fall of
CP1 (Figure 5).
and signals LD0 through LD3 contain the data for the lower screen. For
example, four pixels (UD3:1,1–UD0:1,1) are sent to row 1 at the same time as
four pixels (LD0:1,1–LD3:1,1) are sent to row 241. This results in eight pixels
sent on each cycle of video clock CP2. Pixel information is supplied from left to
right and from top to bottom. Video data for one row is latched on the fall of
CP1 (Figure 5).