Intel 8XC196NP User Manual
8XC196NP, 80C196NU USER’S MANUAL
10-6
The timer/counters can be used as time bases for input captures, output compares, and pro-
grammed interrupts (software timers). When a counter increments from FFFEH to FFFFH or dec-
rements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can
optionally cause an interrupt. The clock source, direction-control source, count direction, and res-
olution of the input capture or output compare are all programmable (see “Programming the Tim-
ers” on page 10-15). The maximum count rate is one-half the internal clock rate, or f/4 (see
“Internal Timing” on page 2-7). This provides a minimum resolution for an input capture or out-
put compare of 160 ns (at f = 25 MHz) for 8XC196NP and 80 ns (at f = 50 MHz) for the
80C196NU.
grammed interrupts (software timers). When a counter increments from FFFEH to FFFFH or dec-
rements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can
optionally cause an interrupt. The clock source, direction-control source, count direction, and res-
olution of the input capture or output compare are all programmable (see “Programming the Tim-
ers” on page 10-15). The maximum count rate is one-half the internal clock rate, or f/4 (see
“Internal Timing” on page 2-7). This provides a minimum resolution for an input capture or out-
put compare of 160 ns (at f = 25 MHz) for 8XC196NP and 80 ns (at f = 50 MHz) for the
80C196NU.
resolution
=
where:
prescaler_divisor
is the clock prescaler divisor from the T
x
CONTROL registers (see
“Timer 1 Control (T1CONTROL) Register” on page 10-16 and
“Timer 2 Control (T2CONTROL) Register” on page 10-17).
“Timer 2 Control (T2CONTROL) Register” on page 10-17).
f
is the internal operating frequency. See “Internal Timing” on page 2-7 for details.
10.3.1 Cascade Mode (Timer 2 Only)
Timer 2 can be used in cascade mode. In this mode, the timer 1 overflow output is used as the
timer 2 clock input. Either the direction control bit of the timer 2 control register or the direction
control assigned to timer 1 controls the count direction. This method, called cascading, can pro-
vide a slow clock for idle mode timeout control or for slow pulse-width modulation (PWM) ap-
plications (see “Generating a Low-speed PWM Output” on page 10-12).
timer 2 clock input. Either the direction control bit of the timer 2 control register or the direction
control assigned to timer 1 controls the count direction. This method, called cascading, can pro-
vide a slow clock for idle mode timeout control or for slow pulse-width modulation (PWM) ap-
plications (see “Generating a Low-speed PWM Output” on page 10-12).
10.3.2 Quadrature Clocking Mode
Both timer 1 and timer 2 can be used in quadrature clocking mode. This mode uses the TxCLK
and TxDIR pins as quadrature inputs, as shown in Figure 10-3. External quadrature-encoded sig-
nals (two signals at the same frequency that differ in phase by 90
and TxDIR pins as quadrature inputs, as shown in Figure 10-3. External quadrature-encoded sig-
nals (two signals at the same frequency that differ in phase by 90
°
) are input, and the timer incre-
ments or decrements by one count on each rising edge and each falling edge. Because the TxCLK
and TxDIR inputs are sampled by the internal phase clocks, transitions must be separated by at
least two state times for proper operation. The count is clocked by PH2, which is PH1 delayed by
one-half period. The sequence of the signal edges and levels controls the count direction. Refer
to Figure 10-4 and Table 10-3 for sequencing information.
and TxDIR inputs are sampled by the internal phase clocks, transitions must be separated by at
least two state times for proper operation. The count is clocked by PH2, which is PH1 delayed by
one-half period. The sequence of the signal edges and levels controls the count direction. Refer
to Figure 10-4 and Table 10-3 for sequencing information.
A typical source of quadrature-encoded signals is a shaft-angle decoder, shown in Figure 10-3.
Its output signals X and Y are input to TxCLK and TxDIR, which in turn output signals
X_internal and Y_internal. These signals are used in Figure 10-4 and Table 10-3 to describe the
direction of the shaft.
Its output signals X and Y are input to TxCLK and TxDIR, which in turn output signals
X_internal and Y_internal. These signals are used in Figure 10-4 and Table 10-3 to describe the
direction of the shaft.
4
p
×
rescaler_divisor
f
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