Intel 8XC196NP User Manual
8XC196NP, 80C196NU USER’S MANUAL
11-10
The simplest way to reset the device is to insert a capacitor between the RESET# pin and V
SS
, as
shown in Figure 11-9. The device has an internal pull-up resistor (R
RST
) shown in Figure 11-8.
RESET# should remain asserted for at least one state time after V
CC
and XTAL1 have stabilized
and met the operating conditions specified in the datasheet. A capacitor of 4.7 µF or greater
should provide sufficient reset time, as long as V
should provide sufficient reset time, as long as V
CC
rises quickly.
Figure 11-9. Minimum Reset Circuit
Other devices in the system may not be reset because the capacitor will keep the voltage above
V
V
IL
. Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer
the system-reset pulse. Figure 11-10 shows an example of a system-reset circuit. In this example,
D2 creates a wired-OR gate connection to the reset pin. An internal reset, system power-up, or
SW1 closing will generate the system-reset signal.
D2 creates a wired-OR gate connection to the reset pin. An internal reset, system power-up, or
SW1 closing will generate the system-reset signal.
Figure 11-10. Example System Reset Circuit
RESET#
8XC196 Device
+
4.7
µ
F
A0276-01
RESET#
8XC196 Device
+
4.7
µ
F
A0276-01
RESET#
8XC196
Device
System reset signal
to external circuitry
(1)
Schmitt Triggers
Notes:
1. D1 provides a faster cycle time for repetitive power-on resets.
2. Optional pull-up for faster recovery.
1. D1 provides a faster cycle time for repetitive power-on resets.
2. Optional pull-up for faster recovery.
R
C
4.7 k
Ω
(2)
D2
SW1
D1
A0277-02
VCC
VCC