Intel 8XC196NP User Manual
Index-3
INDEX
CMP instruction, A-3, A-11, A-49, A-53, A-60
CMPB instruction, A-3, A-12, A-50, A-53, A-60
CMPL instruction, A-2, A-12, A-51, A-53, A-60
Code execution, 2-4, 2-5
Code fetches, 5-25
CompuServe forums, 1-10
Conditional jump instructions, A-5
CON_REG0, C-50, C-53
Constants, near, 5-24
CPU, 2-3
CS5:0#, B-7
CMPB instruction, A-3, A-12, A-50, A-53, A-60
CMPL instruction, A-2, A-12, A-51, A-53, A-60
Code execution, 2-4, 2-5
Code fetches, 5-25
CompuServe forums, 1-10
Conditional jump instructions, A-5
CON_REG0, C-50, C-53
Constants, near, 5-24
CPU, 2-3
CS5:0#, B-7
during bus hold, 13-30
Customer service, 1-8
D
D/A converter, 9-10
Data
Data
far, 5-24
fetches, 5-26
near, 5-24
types, 4-1–4-5
fetches, 5-26
near, 5-24
types, 4-1–4-5
addressing restrictions, 4-1
converting between, 4-4
defined, 4-1
iC-96, 4-1
PLM-96, 4-1
signed and unsigned, 4-1, 4-4
values permitted, 4-1
converting between, 4-4
defined, 4-1
iC-96, 4-1
PLM-96, 4-1
signed and unsigned, 4-1, 4-4
values permitted, 4-1
Data instructions, A-56, A-63
Datasheets
Datasheets
online, 1-10
ordering, 1-7
ordering, 1-7
Deassert, defined, 1-3
DEC instruction, A-2, A-12, A-47, A-53, A-60
DECB instruction, A-2, A-12, A-47, A-53, A-60
DEMUX bit, 13-11, 13-17
Device
DEC instruction, A-2, A-12, A-47, A-53, A-60
DECB instruction, A-2, A-12, A-47, A-53, A-60
DEMUX bit, 13-11, 13-17
Device
minimum hardware configuration, 11-1
reset, 11-8, 11-9, 11-10, 11-11, 13-33
signal descriptions, B-6
reset, 11-8, 11-9, 11-10, 11-11, 13-33
signal descriptions, B-6
DI instruction, A-3, A-13, A-52, A-59, A-67
Digital-to-analog converter, 9-10
Direct addressing, 4-7, 4-11, 5-11
Digital-to-analog converter, 9-10
Direct addressing, 4-7, 4-11, 5-11
and register RAM, 5-11
and windows, 5-13, 5-21
and windows, 5-13, 5-21
DIV instruction, A-13, A-52, A-54, A-61
DIVB instruction, A-13, A-52, A-54, A-61
DIVB instruction, A-13, A-52, A-54, A-61
DIVU instruction, A-3, A-14, A-49, A-54, A-61
DIVUB instruction, A-3, A-14, A-50, A-54, A-61
DJNZ instruction, A-2, A-5, A-14, A-51, A-58,
DIVUB instruction, A-3, A-14, A-50, A-54, A-61
DJNZ instruction, A-2, A-5, A-14, A-51, A-58,
A-66
DJNZW instruction, A-2, A-5, A-15, A-51, A-58,
A-66
Documents, related, 1-5–1-8
DOUBLE-WORD, defined, 4-3
DPTS instruction, A-3, A-15, A-52, A-59, A-67
DOUBLE-WORD, defined, 4-3
DPTS instruction, A-3, A-15, A-52, A-59, A-67
E
EA#, 5-5, 5-6, 5-22, 5-25, 5-26, 13-4, B-8
after reset, 13-18
EBMOVI instruction, 4-5, A-2, A-16, A-51, A-56
EBR (indirect) instruction, 4-5, A-2, A-16, A-51,
EBR (indirect) instruction, 4-5, A-2, A-16, A-51,
A-57, A-64
ECALL instruction, 4-5, A-2, A-17, A-52, A-57,
A-64, A-65
EDAR, 7-13
EE opcode, and unimplemented opcode interrupt,
EE opcode, and unimplemented opcode interrupt,
A-3, A-52
EI instruction, 6-10, A-3, A-17, A-52, A-59, A-67
EJMP instruction, 4-5, A-2, A-17, A-52, A-57,
EJMP instruction, 4-5, A-2, A-17, A-52, A-57,
A-64
ELD instruction, 4-5, A-3, A-18, A-52, A-56, A-63
ELDB instruction, 4-5, A-3, A-18, A-52, A-56,
ELDB instruction, 4-5, A-3, A-18, A-52, A-56,
A-63
EPA, 2-11, 10-1–10-27
and PTS, 10-11
block diagram, 10-2
capture data overruns, 10-21, C-22
capture/compare modules, 10-8
block diagram, 10-2
capture data overruns, 10-21, C-22
capture/compare modules, 10-8
programming, 10-18
choosing capture or compare mode, 10-19,
C-20
compare modules
programming, 10-18
configuring pins, 10-2
controlling the clock source and direction,
controlling the clock source and direction,
10-16, 10-17, C-46, C-47
determining event status, 10-22
enabling a timer/counter, 10-16, 10-17, C-46,
enabling a timer/counter, 10-16, 10-17, C-46,
C-47
enabling remapping for PWM, 10-19, C-20
re-enabling the compare event, 10-20, C-21
resetting the timer in compare mode, 10-21,
re-enabling the compare event, 10-20, C-21
resetting the timer in compare mode, 10-21,
C-22