Intel 8XC196NP User Manual
Index-11
INDEX
T1DIR, 10-2, B-11
T2CLK, 10-2, B-11
T2CONTROL, C-51, C-54
T2DIR, 10-2, B-11
Technical support, 1-11
Terminology, 1-3
TIJMP instruction, A-2, A-44, A-51, A-57, A-64
Timer/counters, 2-11, 10-5, 10-6
T2CLK, 10-2, B-11
T2CONTROL, C-51, C-54
T2DIR, 10-2, B-11
Technical support, 1-11
Terminology, 1-3
TIJMP instruction, A-2, A-44, A-51, A-57, A-64
Timer/counters, 2-11, 10-5, 10-6
and PWM, 10-12, 10-13, 10-14, 10-15
cascading, 10-6
configuring pins, 10-2
count rate, 10-6
resolution, 10-6
SFRs, 10-3
See also EPA
cascading, 10-6
configuring pins, 10-2
count rate, 10-6
resolution, 10-6
SFRs, 10-3
See also EPA
TIMER1, C-51, C-54
TIMER2, C-51, C-54
Timing
TIMER2, C-51, C-54
Timing
HLDA#, 13-30
HOLD#, 13-30
instruction execution, A-60–A-61
internal, 2-7, 2-9
interrupt latency, 6-7–6-10, 6-23
PTS cycles, 6-10
READY, 13-27
SIO port mode 0, 8-5
SIO port mode 1, 8-6
SIO port mode 2, 8-7
SIO port mode 3, 8-7
HOLD#, 13-30
instruction execution, A-60–A-61
internal, 2-7, 2-9
interrupt latency, 6-7–6-10, 6-23
PTS cycles, 6-10
READY, 13-27
SIO port mode 0, 8-5
SIO port mode 1, 8-6
SIO port mode 2, 8-7
SIO port mode 3, 8-7
TRAP instruction, 6-5, A-2, A-45, A-52, A-57,
A-64, A-65
TRAP interrupt, 6-4
TXD, 8-2, B-11
TXD, 8-2, B-11
and SIO port mode 0, 8-4
U
UART, 2-11, 8-1
Unimplemented opcode interrupt, 4-14, 6-4, 6-5,
Unimplemented opcode interrupt, 4-14, 6-4, 6-5,
6-7
Units of measure, defined, 1-5
Universal asynchronous receiver and transmitter‚
Universal asynchronous receiver and transmitter‚
See UART
V
V
CC
, 11-1, B-12
V
SS
, 11-1, B-12
W
Wait states, 13-5, 13-26–13-30
for CCB0 fetch, 13-17
Window selection register‚ See WSR, WSR1
Windows, 5-1, 5-13–5-21
Windows, 5-1, 5-13–5-21
addressing, 5-18
and addressing modes, 5-21
base address, 5-16, 5-18
examples, 5-18–5-21
nonwindowable locations, 5-19
selecting, 5-14
setting up with linker loader, 5-19
table of, 5-15, 5-17
and addressing modes, 5-21
base address, 5-16, 5-18
examples, 5-18–5-21
nonwindowable locations, 5-19
selecting, 5-14
setting up with linker loader, 5-19
table of, 5-15, 5-17
Word accesses, and write-control signals, 13-34
WORD, defined, 4-3
World Wide Web, 1-11
WR#, 13-5, B-12
WORD, defined, 4-3
World Wide Web, 1-11
WR#, 13-5, B-12
after reset, 13-18
during bus hold, 13-30
See also write-control signals
during bus hold, 13-30
See also write-control signals
WRH#, 13-3, 13-5, 13-33, 13-35, B-12
See also write-control signals
Write strobe mode
example, 13-36
Write-control modes, 13-1, 13-33–13-36
byte writes and word writes, 13-35
standard, 13-33
standard, 13-33
Write-control signals, 13-33, 13-34
decoding logic, 13-34
WRL#, 13-5, 13-33, 13-35, B-12
See also write-control signals
WS0 and WS1, 13-11, 13-26
WSR, 5-14, 13-32
WSR1, 5-12, 5-13, 5-15, 5-18
WSR, 5-14, 13-32
WSR1, 5-12, 5-13, 5-15, 5-18
X
X, defined, 1-5
x, defined, 1-4
XCH instruction, A-2, A-3, A-45, A-47, A-56,
x, defined, 1-4
XCH instruction, A-2, A-3, A-45, A-47, A-56,
A-63
XCHB instruction, A-2, A-3, A-45, A-47, A-56,
A-63
XOR instruction, A-2, A-46, A-49, A-54, A-61
XORB instruction, A-2, A-46, A-49, A-50, A-54,
XORB instruction, A-2, A-46, A-49, A-50, A-54,
A-61
XTAL1, 11-2, B-12
and Miller effect, 11-7