Intel 8XC196MD User Manual
6-13
I/O PORTS
P5.0/ALE
If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), either ALE or ADV# is activated as a system
control pin, depending on the ALE bit of CCR0. In either case, the
pin becomes a true complementary output.
until your software writes to P5_MODE. If EA# is low on reset
(external access), either ALE or ADV# is activated as a system
control pin, depending on the ALE bit of CCR0. In either case, the
pin becomes a true complementary output.
P5.1/INST
This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
uration data into P5_MODE.
P5.2/WR#/WRL#
This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
uration data into P5_MODE.
P5.3/RD#
If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), RD# is activated as a system control pin and the
pin becomes a true complementary output.
until your software writes to P5_MODE. If EA# is low on reset
(external access), RD# is activated as a system control pin and the
pin becomes a true complementary output.
P5.4
This pin is weakly held high until your software writes to
P5_MODE. P5.4 is the enable pin for ONCE mode (see Chapter 14,
“Special Operating Modes”) and one of the enable pins for Intel-
reserved test modes. Because a low input during reset could cause the
device to enter ONCE mode or a reserved test mode, exercise
caution if you use this pin for input. Be certain that your system
meets the V
P5_MODE. P5.4 is the enable pin for ONCE mode (see Chapter 14,
“Special Operating Modes”) and one of the enable pins for Intel-
reserved test modes. Because a low input during reset could cause the
device to enter ONCE mode or a reserved test mode, exercise
caution if you use this pin for input. Be certain that your system
meets the V
IH
specification (listed in the datasheet) during reset to
prevent inadvertent entry into ONCE mode or a test mode.
P5.5/BHE#/WRH#
This pin is weakly held high until the CCB fetch is completed. At
that time, the state of this pin depends on the value of the BW0 bit of
the CCRs. If BW0 is clear, the pin remains weakly held high until
your software writes to P5_MODE. If BW0 is set, BHE# is activated
as a system control pin and the pin becomes a true complementary
output.
that time, the state of this pin depends on the value of the BW0 bit of
the CCRs. If BW0 is clear, the pin remains weakly held high until
your software writes to P5_MODE. If BW0 is set, BHE# is activated
as a system control pin and the pin becomes a true complementary
output.
P5.6/READY
This pin remains weakly held high until the CCB fetch is completed.
At that time, the state of this pin depends on the value of the IRC0–
IRC2 bits of the CCRs. If IRC0–IRC2 are all set (111B), READY is
activated as a system control pin. This prevents the insertion of
infinite wait states upon the first access to external memory. For any
other values of IRC0–IRC2, the pin is configured as I/O upon reset.
At that time, the state of this pin depends on the value of the IRC0–
IRC2 bits of the CCRs. If IRC0–IRC2 are all set (111B), READY is
activated as a system control pin. This prevents the insertion of
infinite wait states upon the first access to external memory. For any
other values of IRC0–IRC2, the pin is configured as I/O upon reset.
NOTE:
If IRC0–IRC2 of the CCB are all set (activating READY as
a system control pin) and P5_MODE.6 is cleared (config-
uring the pin as I/O), an external memory access may cause
the processor to lock up.
a system control pin) and P5_MODE.6 is cleared (config-
uring the pin as I/O), an external memory access may cause
the processor to lock up.
P5.7/BUSWIDTH
This pin remains weakly held high until your software writes config-
uration data into P5_MODE.