Intel 8XC196MD User Manual
A-51
INSTRUCTION SET REFERENCE
Shift
Mnemonic
Direct
Immediate
Indirect Indexed
Length
Opcode
Length
Opcode
Length
Opcode
Length
Opcode
NORML
3
0F
—
—
—
—
—
—
SHL
3
09
—
—
—
—
—
—
SHLB
3
19
—
—
—
—
—
—
SHLL
3
0D
—
—
—
—
—
—
SHR
3
08
—
—
—
—
—
—
SHRA
3
0A
—
—
—
—
—
—
SHRAB
3
1A
—
—
—
—
—
—
SHRAL
3
0E
—
—
—
—
—
—
SHRB
3
18
—
—
—
—
—
—
SHRL
3
0C
—
—
—
—
—
—
Special
Mnemonic
Direct
Immediate
Indirect Indexed
Length
Opcode
Length
Opcode
Length
Opcode
Length
Opcode
CLRC
1
F8
—
—
—
—
—
—
CLRVT
1
FC
—
—
—
—
—
—
DI
1
FA
—
—
—
—
—
—
EI
1
FB
—
—
—
—
—
—
IDLPD
—
—
1
F6
—
—
—
—
NOP
1
FD
—
—
—
—
—
—
RST
1
FF
—
—
—
—
—
—
SETC
1
F9
—
—
—
—
—
—
SKIP
2
00
—
—
—
—
—
—
PTS
Mnemonic
Direct
Immediate
Indirect Indexed
Length
Opcode
Length
Opcode
Length
Opcode
Length
Opcode
DPTS
1
EC
—
—
—
—
—
—
EPTS
1
ED
—
—
—
—
—
—
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1.
1.
For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
2.
For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, two’s complement offset.
with the eight bits to form an 11-bit, two’s complement offset.