Samsung S3C8245 User Manual
S3C8245/P8245/C8249/P8249
8-BIT TIMER A/B
11-3
TIMER A CONTROL REGISTER (TACON)
You use the timer A control register, TACON, to
— Select the timer A operating mode (interval timer, capture mode, or PWM mode)
— Select the timer A input clock frequency
— Clear the timer A counter, TACNT
— Enable the timer A overflow interrupt or timer A match/capture interrupt
— Clear timer A match/capture interrupt pending conditions
TACON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode.
A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of
fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.3.
fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.3.
The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address E2H. When a timer A
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.
Timer A Control Register (TACON)
EDH, Set 1, Bank 0, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Timer A match/capture interrupt
enable bit:
0 = DIsable interrupt
1 = Enable interrupt
enable bit:
0 = DIsable interrupt
1 = Enable interrupt
Timer A match/capture interrupt
pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending
pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending
Timer A overflow interrupt enable:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer A counter clear bit:
0 = No affect
1 = Clear the timer A counter (when write)
0 = No affect
1 = Clear the timer A counter (when write)
Timer A input clock selection bits:
00 = f
00 = f
XX
/1024
01 = f
XX
/256
10 = f
XX
/64
11 = External clock (TACLK)
Timer A operating mode selection bits:
00 = Interval mode (TAOUT mode)
01 = Capture mode (capture on rising edge,
Counter running, OVF can occur)
10 = Capture mode (Capture on falling edge,
Counter running, OVF can occur)
11 = PWM mode (OVF interrupt can occur)
00 = Interval mode (TAOUT mode)
01 = Capture mode (capture on rising edge,
Counter running, OVF can occur)
10 = Capture mode (Capture on falling edge,
Counter running, OVF can occur)
11 = PWM mode (OVF interrupt can occur)
Figure 11-1. Timer A Control Register (TACON)