Samsung S3C8245 User Manual
S3C8245/P8245/C8249/P8249
16-BIT TIMER 0/1
12-9
Timer 1 Counter Register, High-Byte (T1CNTH)
FCH, Set 1, Bank 1, R
MSB
LSB
Reset Value: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 Counter Register, Low-Byte (T1CNTL)
FDH, Set 1, Bank 1, R
Reset Value: 00H
Figure 12-7. Timer 1 Control Register (T1CNTH/L)
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 Data Register,High-Byte (T1DATAH)
FEH, Set 1, Bank 1, R/W
Reset Value: FFh
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 Data Register, Low-Byte (T1DATAL)
FFH, Set 1, Bank 1, R/W
Reset Value: FFh
MSB
NOTE:
Pending bit is located in INTPND (D2H, set1) register.
Figure 12-8. Timer 1 Data Register (T1DATAH/L)