Intel 80C196NU User Manual
8-7
SERIAL I/O (SIO) PORT
8.3.2.2
Mode 2
Mode 2 is the asynchronous, ninth-bit recognition mode. This mode is commonly used with mode
3 for multiprocessor communications. Figure 8-5 shows the data frame used in this mode. It con-
sists of a start bit (0), nine data bits (LSB first), and a stop bit (1). During transmissions, setting
the TB8 bit in the SP_CON register before writing to SBUF_TX sets the ninth transmission bit.
The hardware clears the TB8 bit after every transmission, so it must be set (if desired) before each
write to SBUF_TX. During receptions, the RI flag and RI interrupt pending bit are set only if the
TB8 bit is set. This provides an easy way to have selective reception on a data link. (See “Multi-
processor Communications” on page 8-8). Parity cannot be enabled in this mode.
3 for multiprocessor communications. Figure 8-5 shows the data frame used in this mode. It con-
sists of a start bit (0), nine data bits (LSB first), and a stop bit (1). During transmissions, setting
the TB8 bit in the SP_CON register before writing to SBUF_TX sets the ninth transmission bit.
The hardware clears the TB8 bit after every transmission, so it must be set (if desired) before each
write to SBUF_TX. During receptions, the RI flag and RI interrupt pending bit are set only if the
TB8 bit is set. This provides an easy way to have selective reception on a data link. (See “Multi-
processor Communications” on page 8-8). Parity cannot be enabled in this mode.
Figure 8-5. Serial Port Frames in Mode 2 and 3
8.3.2.3
Mode 3
Mode 3 is the asynchronous, ninth-bit mode. The data frame for this mode is identical to that of
mode 2. Mode 3 differs from mode 2 during transmissions in that parity can be enabled, in which
case the ninth bit becomes the parity bit. When parity is disabled, data bits 0–7 are written to the
serial port transmit buffer, and the ninth data bit is written to bit 4 (TB8) bit in the SP_CON reg-
ister. In mode 3, a reception always sets the RI interrupt pending bit, regardless of the state of the
ninth bit. If parity is disabled, the SP_STATUS register bit 7 (RB8) contains the ninth data bit. If
parity is enabled, then bit 7 (RB8) is the received parity error (RPE) flag.
mode 2. Mode 3 differs from mode 2 during transmissions in that parity can be enabled, in which
case the ninth bit becomes the parity bit. When parity is disabled, data bits 0–7 are written to the
serial port transmit buffer, and the ninth data bit is written to bit 4 (TB8) bit in the SP_CON reg-
ister. In mode 3, a reception always sets the RI interrupt pending bit, regardless of the state of the
ninth bit. If parity is disabled, the SP_STATUS register bit 7 (RB8) contains the ninth data bit. If
parity is enabled, then bit 7 (RB8) is the received parity error (RPE) flag.
8.3.2.4
Mode 2 and 3 Timings
Operation in modes 2 and 3 is similar to mode 1 operation. The only difference is that the data
consists of 9 bits, so 11-bit packages are transmitted and received. During a reception, the RI flag
and the RI interrupt pending bit are set just after the end of the stop bit. During a transmission,
the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit. The ninth bit
can be used for parity or multiprocessor communications.
consists of 9 bits, so 11-bit packages are transmitted and received. During a reception, the RI flag
and the RI interrupt pending bit are set just after the end of the stop bit. During a transmission,
the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit. The ninth bit
can be used for parity or multiprocessor communications.
Start
Stop
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
8 Bits of Data
11-Bit Frame
Programmable 9th Bit
A0111-01