Intel 80C196NU User Manual
12-7
SPECIAL OPERATING MODES
12.4.3 Exiting Standby Mode
The device will exit standby mode when a transition on an external interrupt pin (EXTINT3:0)
or a hardware reset occurs. The interrupts need not be enabled for them to bring the device out of
standby, but the pin must be configured as a special-function input (see “Bidirectional Port Pin
Configurations” on page 7-7).
or a hardware reset occurs. The interrupts need not be enabled for them to bring the device out of
standby, but the pin must be configured as a special-function input (see “Bidirectional Port Pin
Configurations” on page 7-7).
When an external interrupt brings the device out of standby mode, the corresponding pending bit
is set in the interrupt pending register. If the interrupt is enabled, the device executes the interrupt
service routine, then fetches and executes the instruction following the IDLPD #3 instruction. If
the interrupt is disabled (masked), the device fetches and executes the instruction following the
IDLPD #3 instruction and the pending bit remains set until the interrupt is serviced or software
clears it.
is set in the interrupt pending register. If the interrupt is enabled, the device executes the interrupt
service routine, then fetches and executes the instruction following the IDLPD #3 instruction. If
the interrupt is disabled (masked), the device fetches and executes the instruction following the
IDLPD #3 instruction and the pending bit remains set until the interrupt is serviced or software
clears it.
12.5 POWERDOWN MODE
Powerdown mode places the device into a very low power state by disabling the internal oscilla-
tor, the phase-locked loop circuitry (80C196NU only), and clock generators. Internal logic holds
the CPU and peripheral clocks at logic zero, which causes the CPU to stop executing instructions,
the system bus-control signals to become inactive, the CLKOUT signal to become high, and the
peripherals to turn off. Power consumption drops into the microwatt range (refer to the datasheet
for exact specifications). I
tor, the phase-locked loop circuitry (80C196NU only), and clock generators. Internal logic holds
the CPU and peripheral clocks at logic zero, which causes the CPU to stop executing instructions,
the system bus-control signals to become inactive, the CLKOUT signal to become high, and the
peripherals to turn off. Power consumption drops into the microwatt range (refer to the datasheet
for exact specifications). I
CC
is reduced to device leakage. Table B-5 on page B-13 lists the values
of the pins during powerdown mode. If V
CC
is maintained above the minimum specification, the
special-function registers (SFRs) and register RAM retain their data.
12.5.1 Enabling and Disabling Powerdown Mode
Setting the PD bit in the chip-configuration register 0 (CCR0.0) enables both standby and pow-
erdown modes. Clearing it disables both modes. CCR0 is loaded from the chip configuration byte
(CCB0) when the device is reset.
erdown modes. Clearing it disables both modes. CCR0 is loaded from the chip configuration byte
(CCB0) when the device is reset.
12.5.2 Entering Powerdown Mode
Before entering powerdown, complete the following tasks:
•
Complete all serial port transmissions or receptions. Otherwise, when the device exits
powerdown, the serial port activity will continue where it left off and incorrect data may be
transmitted or received.
powerdown, the serial port activity will continue where it left off and incorrect data may be
transmitted or received.
•
Put all other peripherals into an inactive state.
•
To allow other devices to control the bus while the microcontroller is in powerdown, assert
HLDA#. Do this only if the routines for entering and exiting powerdown do not require
access to external memory.
HLDA#. Do this only if the routines for entering and exiting powerdown do not require
access to external memory.