Intel 80C196NU User Manual
8XC196NP, 80C196NU USER’S MANUAL
13-14
13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES
Two chip configuration registers (CCRs) have bits that set parameters for chip operation and ex-
ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-
uration bytes (CCBs), which have internal addresses FF2018H (CCB0) and FF201AH (CCB1).
If the CCBs are stored in external memory, their external addresses depend on the number of
EPORT lines used in the external system (see “Internal and External Addresses” on page 13-1).
ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-
uration bytes (CCBs), which have internal addresses FF2018H (CCB0) and FF201AH (CCB1).
If the CCBs are stored in external memory, their external addresses depend on the number of
EPORT lines used in the external system (see “Internal and External Addresses” on page 13-1).
When the device returns from reset, the bus controller fetches the CCBs and loads them into the
CCRs. From this point, these CCR bit values define the chip configuration until the device is reset
again. The CCR bits are described in Figures 13-6 and 13-7. The remainder of this section de-
scribes the state of the chip following reset and the process of fetching the CCBs.
CCRs. From this point, these CCR bit values define the chip configuration until the device is reset
again. The CCR bits are described in Figures 13-6 and 13-7. The remainder of this section de-
scribes the state of the chip following reset and the process of fetching the CCBs.
Table 13-9. Results for the Chip-select Example
Chip
Select
Address
Range
Size of
Address Range
Number of
Bits to Set in
ADDRMSK
x
Contents of
ADDRCOM
x
Contents of
ADDRMSK
x
0
80000–FFFFFH
512 Kbytes = 2
19
bytes
n
1
= 20 – 19 = 1
0800H
0800H
1
01E00–01EFFH
256 bytes = 2
8
bytes
n
1
= 20 – 8 = 12
001EH
0FFFH
2
7E000–7FFFFH
8 Kbytes = 2
13
bytes
n
1
= 20 – 13 = 7
07E0H
0FE0H